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Move QOM typedefs and add missing includes

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Some typedefs and macros are defined after the type check macros.
This makes it difficult to automatically replace their
definitions with OBJECT_DECLARE_TYPE.

Patch generated using:

 $ ./scripts/codeconverter/converter.py -i \
   --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')

which will split "typdef struct { ... } TypedefName"
declarations.

Followed by:

 $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \
    $(git grep -l '' -- '*.[ch]')

which will:
- move the typedefs and #defines above the type check macros
- add missing #include "qom/object.h" lines if necessary

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-9-ehabkost@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-10-ehabkost@redhat.com>
Message-Id: <20200831210740.126168-11-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Eduardo Habkost 2020-09-03 16:43:22 -04:00
parent 1c8eef0227
commit db1015e92e
796 changed files with 3378 additions and 1823 deletions
Download patch file Download diff file Expand all files Collapse all files

5
include/hw/acpi/acpi_dev_interface.h
View file

@ -18,6 +18,7 @@ typedef enum {
#define TYPE_ACPI_DEVICE_IF "acpi-device-interface"
typedef struct AcpiDeviceIfClass AcpiDeviceIfClass;
#define ACPI_DEVICE_IF_CLASS(klass) \
OBJECT_CLASS_CHECK(AcpiDeviceIfClass, (klass), \
TYPE_ACPI_DEVICE_IF)
@ -48,7 +49,7 @@ void acpi_send_event(DeviceState *dev, AcpiEventStatusBits event);
* knowledge about internals of actual device that implements
* ACPI interface.
*/
typedef struct AcpiDeviceIfClass {
struct AcpiDeviceIfClass {
/* <private> */
InterfaceClass parent_class;
@ -57,5 +58,5 @@ typedef struct AcpiDeviceIfClass {
void (*send_event)(AcpiDeviceIf *adev, AcpiEventStatusBits ev);
void (*madt_cpu)(AcpiDeviceIf *adev, int uid,
const CPUArchIdList *apic_ids, GArray *entry);
} AcpiDeviceIfClass;
};
#endif

6
include/hw/acpi/generic_event_device.h
View file

@ -62,10 +62,12 @@
#include "hw/sysbus.h"
#include "hw/acpi/memory_hotplug.h"
#include "hw/acpi/ghes.h"
#include "qom/object.h"
#define ACPI_POWER_BUTTON_DEVICE "PWRB"
#define TYPE_ACPI_GED "acpi-ged"
typedef struct AcpiGedState AcpiGedState;
#define ACPI_GED(obj) \
OBJECT_CHECK(AcpiGedState, (obj), TYPE_ACPI_GED)
@ -90,7 +92,7 @@ typedef struct GEDState {
uint32_t sel;
} GEDState;
typedef struct AcpiGedState {
struct AcpiGedState {
SysBusDevice parent_obj;
MemHotplugState memhp_state;
MemoryRegion container_memhp;
@ -98,7 +100,7 @@ typedef struct AcpiGedState {
uint32_t ged_event_bitmap;
qemu_irq irq;
AcpiGhesState ghes_state;
} AcpiGedState;
};
void build_ged_aml(Aml *table, const char* name, HotplugHandler *hotplug_dev,
uint32_t ged_irq, AmlRegionSpace rs, hwaddr ged_base);

6
include/hw/acpi/vmgenid.h
View file

@ -4,6 +4,7 @@
#include "hw/acpi/bios-linker-loader.h"
#include "hw/qdev-core.h"
#include "qemu/uuid.h"
#include "qom/object.h"
#define VMGENID_DEVICE "vmgenid"
#define VMGENID_GUID "guid"
@ -15,13 +16,14 @@
* OVMF SDT Header Probe Supressor
*/
typedef struct VmGenIdState VmGenIdState;
#define VMGENID(obj) OBJECT_CHECK(VmGenIdState, (obj), VMGENID_DEVICE)
typedef struct VmGenIdState {
struct VmGenIdState {
DeviceClass parent_obj;
QemuUUID guid; /* The 128-bit GUID seen by the guest */
uint8_t vmgenid_addr_le[8]; /* Address of the GUID (little-endian) */
} VmGenIdState;
};
/* returns NULL unless there is exactly one device */
static inline Object *find_vmgenid_dev(void)

6
include/hw/adc/stm32f2xx_adc.h
View file

@ -26,6 +26,7 @@
#define HW_STM32F2XX_ADC_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define ADC_SR 0x00
#define ADC_CR1 0x04
@ -58,10 +59,11 @@
#define ADC_COMMON_ADDRESS 0x100
#define TYPE_STM32F2XX_ADC "stm32f2xx-adc"
typedef struct STM32F2XXADCState STM32F2XXADCState;
#define STM32F2XX_ADC(obj) \
OBJECT_CHECK(STM32F2XXADCState, (obj), TYPE_STM32F2XX_ADC)
typedef struct {
struct STM32F2XXADCState {
/* <private> */
SysBusDevice parent_obj;
@ -84,6 +86,6 @@ typedef struct {
uint32_t adc_dr;
qemu_irq irq;
} STM32F2XXADCState;
};
#endif /* HW_STM32F2XX_ADC_H */

6
include/hw/arm/allwinner-a10.h
View file

@ -14,6 +14,7 @@
#include "hw/rtc/allwinner-rtc.h"
#include "target/arm/cpu.h"
#include "qom/object.h"
#define AW_A10_SDRAM_BASE 0x40000000
@ -21,9 +22,10 @@
#define AW_A10_NUM_USB 2
#define TYPE_AW_A10 "allwinner-a10"
typedef struct AwA10State AwA10State;
#define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10)
typedef struct AwA10State {
struct AwA10State {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
@ -38,6 +40,6 @@ typedef struct AwA10State {
MemoryRegion sram_a;
EHCISysBusState ehci[AW_A10_NUM_USB];
OHCISysBusState ohci[AW_A10_NUM_USB];
} AwA10State;
};
#endif

5
include/hw/arm/allwinner-h3.h
View file

@ -106,6 +106,7 @@ enum {
#define TYPE_AW_H3 "allwinner-h3"
/** Convert input object to Allwinner H3 state object */
typedef struct AwH3State AwH3State;
#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
/** @} */
@ -116,7 +117,7 @@ enum {
* This struct contains the state of all the devices
* which are currently emulated by the H3 SoC code.
*/
typedef struct AwH3State {
struct AwH3State {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
@ -136,7 +137,7 @@ typedef struct AwH3State {
MemoryRegion sram_a1;
MemoryRegion sram_a2;
MemoryRegion sram_c;
} AwH3State;
};
/**
* Emulate Boot ROM firmware setup functionality.

11
include/hw/arm/armsse.h
View file

@ -105,8 +105,11 @@
#include "hw/or-irq.h"
#include "hw/core/split-irq.h"
#include "hw/cpu/cluster.h"
#include "qom/object.h"
#define TYPE_ARM_SSE "arm-sse"
typedef struct ARMSSE ARMSSE;
typedef struct ARMSSEClass ARMSSEClass;
#define ARM_SSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARM_SSE)
/*
@ -140,7 +143,7 @@
#define RAM3_PPU 6
#define NUM_PPUS 7
typedef struct ARMSSE {
struct ARMSSE {
/*< private >*/
SysBusDevice parent_obj;
@ -215,14 +218,14 @@ typedef struct ARMSSE {
uint32_t init_svtor;
bool cpu_fpu[SSE_MAX_CPUS];
bool cpu_dsp[SSE_MAX_CPUS];
} ARMSSE;
};
typedef struct ARMSSEInfo ARMSSEInfo;
typedef struct ARMSSEClass {
struct ARMSSEClass {
SysBusDeviceClass parent_class;
const ARMSSEInfo *info;
} ARMSSEClass;
};
#define ARM_SSE_CLASS(klass) \
OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARM_SSE)

11
include/hw/arm/armv7m.h
View file

@ -13,11 +13,13 @@
#include "hw/sysbus.h"
#include "hw/intc/armv7m_nvic.h"
#include "target/arm/idau.h"
#include "qom/object.h"
#define TYPE_BITBAND "ARM,bitband-memory"
typedef struct BitBandState BitBandState;
#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
typedef struct {
struct BitBandState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -26,9 +28,10 @@ typedef struct {
MemoryRegion iomem;
uint32_t base;
MemoryRegion *source_memory;
} BitBandState;
};
#define TYPE_ARMV7M "armv7m"
typedef struct ARMv7MState ARMv7MState;
#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
#define ARMV7M_NUM_BITBANDS 2
@ -49,7 +52,7 @@ typedef struct {
* + Property "dsp": enable DSP (forwarded to CPU object)
* + Property "enable-bitband": expose bitbanded IO
*/
typedef struct ARMv7MState {
struct ARMv7MState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -72,6 +75,6 @@ typedef struct ARMv7MState {
bool start_powered_off;
bool vfp;
bool dsp;
} ARMv7MState;
};
#endif

6
include/hw/arm/aspeed.h
View file

@ -10,10 +10,12 @@
#define ARM_ASPEED_H
#include "hw/boards.h"
#include "qom/object.h"
typedef struct AspeedMachineState AspeedMachineState;
#define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed")
typedef struct AspeedMachineClass AspeedMachineClass;
#define ASPEED_MACHINE(obj) \
OBJECT_CHECK(AspeedMachineState, (obj), TYPE_ASPEED_MACHINE)
@ -27,7 +29,7 @@ typedef struct AspeedMachineState AspeedMachineState;
#define ASPEED_MACHINE_GET_CLASS(obj) \
OBJECT_GET_CLASS(AspeedMachineClass, (obj), TYPE_ASPEED_MACHINE)
typedef struct AspeedMachineClass {
struct AspeedMachineClass {
MachineClass parent_obj;
const char *name;
@ -40,7 +42,7 @@ typedef struct AspeedMachineClass {
uint32_t num_cs;
uint32_t macs_mask;
void (*i2c_init)(AspeedMachineState *bmc);
} AspeedMachineClass;
};
#endif

11
include/hw/arm/aspeed_soc.h
View file

@ -27,6 +27,7 @@
#include "hw/gpio/aspeed_gpio.h"
#include "hw/sd/aspeed_sdhci.h"
#include "hw/usb/hcd-ehci.h"
#include "qom/object.h"
#define ASPEED_SPIS_NUM 2
#define ASPEED_EHCIS_NUM 2
@ -34,7 +35,7 @@
#define ASPEED_CPUS_NUM 2
#define ASPEED_MACS_NUM 4
typedef struct AspeedSoCState {
struct AspeedSoCState {
/*< private >*/
DeviceState parent;
@ -60,12 +61,14 @@ typedef struct AspeedSoCState {
AspeedGPIOState gpio_1_8v;
AspeedSDHCIState sdhci;
AspeedSDHCIState emmc;
} AspeedSoCState;
};
typedef struct AspeedSoCState AspeedSoCState;
#define TYPE_ASPEED_SOC "aspeed-soc"
typedef struct AspeedSoCClass AspeedSoCClass;
#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
typedef struct AspeedSoCClass {
struct AspeedSoCClass {
DeviceClass parent_class;
const char *name;
@ -79,7 +82,7 @@ typedef struct AspeedSoCClass {
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
} AspeedSoCClass;
};
#define ASPEED_SOC_CLASS(klass) \
OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)

6
include/hw/arm/bcm2835_peripherals.h
View file

@ -29,12 +29,14 @@
#include "hw/timer/bcm2835_systmr.h"
#include "hw/usb/hcd-dwc2.h"
#include "hw/misc/unimp.h"
#include "qom/object.h"
#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
typedef struct BCM2835PeripheralState BCM2835PeripheralState;
#define BCM2835_PERIPHERALS(obj) \
OBJECT_CHECK(BCM2835PeripheralState, (obj), TYPE_BCM2835_PERIPHERALS)
typedef struct BCM2835PeripheralState {
struct BCM2835PeripheralState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -70,6 +72,6 @@ typedef struct BCM2835PeripheralState {
UnimplementedDeviceState smi;
DWC2State dwc2;
UnimplementedDeviceState sdramc;
} BCM2835PeripheralState;
};
#endif /* BCM2835_PERIPHERALS_H */

11
include/hw/arm/bcm2836.h
View file

@ -15,8 +15,11 @@
#include "hw/arm/bcm2835_peripherals.h"
#include "hw/intc/bcm2836_control.h"
#include "target/arm/cpu.h"
#include "qom/object.h"
#define TYPE_BCM283X "bcm283x"
typedef struct BCM283XClass BCM283XClass;
typedef struct BCM283XState BCM283XState;
#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
#define BCM283X_NCPUS 4
@ -28,7 +31,7 @@
#define TYPE_BCM2836 "bcm2836"
#define TYPE_BCM2837 "bcm2837"
typedef struct BCM283XState {
struct BCM283XState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
@ -40,14 +43,14 @@ typedef struct BCM283XState {
} cpu[BCM283X_NCPUS];
BCM2836ControlState control;
BCM2835PeripheralState peripherals;
} BCM283XState;
};
typedef struct BCM283XInfo BCM283XInfo;
typedef struct BCM283XClass {
struct BCM283XClass {
DeviceClass parent_class;
const BCM283XInfo *info;
} BCM283XClass;
};
#define BCM283X_CLASS(klass) \
OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)

6
include/hw/arm/digic.h
View file

@ -21,14 +21,16 @@
#include "cpu.h"
#include "hw/timer/digic-timer.h"
#include "hw/char/digic-uart.h"
#include "qom/object.h"
#define TYPE_DIGIC "digic"
typedef struct DigicState DigicState;
#define DIGIC(obj) OBJECT_CHECK(DigicState, (obj), TYPE_DIGIC)
#define DIGIC4_NB_TIMERS 3
typedef struct DigicState {
struct DigicState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
@ -37,6 +39,6 @@ typedef struct DigicState {
DigicTimerState timer[DIGIC4_NB_TIMERS];
DigicUartState uart;
} DigicState;
};
#endif /* HW_ARM_DIGIC_H */

6
include/hw/arm/exynos4210.h
View file

@ -27,6 +27,7 @@
#include "hw/or-irq.h"
#include "hw/sysbus.h"
#include "target/arm/cpu-qom.h"
#include "qom/object.h"
#define EXYNOS4210_NCPUS 2
@ -85,7 +86,7 @@ typedef struct Exynos4210Irq {
qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
} Exynos4210Irq;
typedef struct Exynos4210State {
struct Exynos4210State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -101,7 +102,8 @@ typedef struct Exynos4210State {
MemoryRegion bootreg_mem;
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
} Exynos4210State;
};
typedef struct Exynos4210State Exynos4210State;
#define TYPE_EXYNOS4210_SOC "exynos4210"
#define EXYNOS4210_SOC(obj) \

6
include/hw/arm/fsl-imx25.h
View file

@ -32,8 +32,10 @@
#include "hw/watchdog/wdt_imx2.h"
#include "exec/memory.h"
#include "target/arm/cpu.h"
#include "qom/object.h"
#define TYPE_FSL_IMX25 "fsl,imx25"
typedef struct FslIMX25State FslIMX25State;
#define FSL_IMX25(obj) OBJECT_CHECK(FslIMX25State, (obj), TYPE_FSL_IMX25)
#define FSL_IMX25_NUM_UARTS 5
@ -44,7 +46,7 @@
#define FSL_IMX25_NUM_ESDHCS 2
#define FSL_IMX25_NUM_USBS 2
typedef struct FslIMX25State {
struct FslIMX25State {
/*< private >*/
DeviceState parent_obj;
@ -66,7 +68,7 @@ typedef struct FslIMX25State {
MemoryRegion iram;
MemoryRegion iram_alias;
uint32_t phy_num;
} FslIMX25State;
};
/**
* i.MX25 memory map

6
include/hw/arm/fsl-imx31.h
View file

@ -28,8 +28,10 @@
#include "hw/watchdog/wdt_imx2.h"
#include "exec/memory.h"
#include "target/arm/cpu.h"
#include "qom/object.h"
#define TYPE_FSL_IMX31 "fsl,imx31"
typedef struct FslIMX31State FslIMX31State;
#define FSL_IMX31(obj) OBJECT_CHECK(FslIMX31State, (obj), TYPE_FSL_IMX31)
#define FSL_IMX31_NUM_UARTS 2
@ -37,7 +39,7 @@
#define FSL_IMX31_NUM_I2CS 3
#define FSL_IMX31_NUM_GPIOS 3
typedef struct FslIMX31State {
struct FslIMX31State {
/*< private >*/
DeviceState parent_obj;
@ -55,7 +57,7 @@ typedef struct FslIMX31State {
MemoryRegion rom;
MemoryRegion iram;
MemoryRegion iram_alias;
} FslIMX31State;
};
#define FSL_IMX31_SECURE_ROM_ADDR 0x00000000
#define FSL_IMX31_SECURE_ROM_SIZE 0x4000

6
include/hw/arm/fsl-imx6.h
View file

@ -34,8 +34,10 @@
#include "hw/usb/imx-usb-phy.h"
#include "exec/memory.h"
#include "cpu.h"
#include "qom/object.h"
#define TYPE_FSL_IMX6 "fsl,imx6"
typedef struct FslIMX6State FslIMX6State;
#define FSL_IMX6(obj) OBJECT_CHECK(FslIMX6State, (obj), TYPE_FSL_IMX6)
#define FSL_IMX6_NUM_CPUS 4
@ -49,7 +51,7 @@
#define FSL_IMX6_NUM_USB_PHYS 2
#define FSL_IMX6_NUM_USBS 4
typedef struct FslIMX6State {
struct FslIMX6State {
/*< private >*/
DeviceState parent_obj;
@ -74,7 +76,7 @@ typedef struct FslIMX6State {
MemoryRegion ocram;
MemoryRegion ocram_alias;
uint32_t phy_num;
} FslIMX6State;
};
#define FSL_IMX6_MMDC_ADDR 0x10000000

6
include/hw/arm/fsl-imx6ul.h
View file

@ -38,8 +38,10 @@
#include "hw/usb/imx-usb-phy.h"
#include "exec/memory.h"
#include "cpu.h"
#include "qom/object.h"
#define TYPE_FSL_IMX6UL "fsl,imx6ul"
typedef struct FslIMX6ULState FslIMX6ULState;
#define FSL_IMX6UL(obj) OBJECT_CHECK(FslIMX6ULState, (obj), TYPE_FSL_IMX6UL)
enum FslIMX6ULConfiguration {
@ -60,7 +62,7 @@ enum FslIMX6ULConfiguration {
FSL_IMX6UL_NUM_USBS = 2,
};
typedef struct FslIMX6ULState {
struct FslIMX6ULState {
/*< private >*/
DeviceState parent_obj;
@ -89,7 +91,7 @@ typedef struct FslIMX6ULState {
MemoryRegion ocram_alias;
uint32_t phy_num[FSL_IMX6UL_NUM_ETHS];
} FslIMX6ULState;
};
enum FslIMX6ULMemoryMap {
FSL_IMX6UL_MMDC_ADDR = 0x80000000,

6
include/hw/arm/fsl-imx7.h
View file

@ -39,8 +39,10 @@
#include "hw/pci-host/designware.h"
#include "hw/usb/chipidea.h"
#include "cpu.h"
#include "qom/object.h"
#define TYPE_FSL_IMX7 "fsl,imx7"
typedef struct FslIMX7State FslIMX7State;
#define FSL_IMX7(obj) OBJECT_CHECK(FslIMX7State, (obj), TYPE_FSL_IMX7)
enum FslIMX7Configuration {
@ -59,7 +61,7 @@ enum FslIMX7Configuration {
FSL_IMX7_NUM_ADCS = 2,
};
typedef struct FslIMX7State {
struct FslIMX7State {
/*< private >*/
DeviceState parent_obj;
@ -82,7 +84,7 @@ typedef struct FslIMX7State {
ChipideaState usb[FSL_IMX7_NUM_USBS];
DesignwarePCIEHost pcie;
uint32_t phy_num[FSL_IMX7_NUM_ETHS];
} FslIMX7State;
};
enum FslIMX7MemoryMap {
FSL_IMX7_MMDC_ADDR = 0x80000000,

5
include/hw/arm/linux-boot-if.h
View file

@ -9,6 +9,7 @@
#include "qom/object.h"
#define TYPE_ARM_LINUX_BOOT_IF "arm-linux-boot-if"
typedef struct ARMLinuxBootIfClass ARMLinuxBootIfClass;
#define ARM_LINUX_BOOT_IF_CLASS(klass) \
OBJECT_CLASS_CHECK(ARMLinuxBootIfClass, (klass), TYPE_ARM_LINUX_BOOT_IF)
#define ARM_LINUX_BOOT_IF_GET_CLASS(obj) \
@ -18,7 +19,7 @@
typedef struct ARMLinuxBootIf ARMLinuxBootIf;
typedef struct ARMLinuxBootIfClass {
struct ARMLinuxBootIfClass {
/*< private >*/
InterfaceClass parent_class;
@ -35,6 +36,6 @@ typedef struct ARMLinuxBootIfClass {
* (or for a CPU which doesn't support TrustZone)
*/
void (*arm_linux_init)(ARMLinuxBootIf *obj, bool secure_boot);
} ARMLinuxBootIfClass;
};
#endif

6
include/hw/arm/msf2-soc.h
View file

@ -30,8 +30,10 @@
#include "hw/misc/msf2-sysreg.h"
#include "hw/ssi/mss-spi.h"
#include "hw/net/msf2-emac.h"
#include "qom/object.h"
#define TYPE_MSF2_SOC "msf2-soc"
typedef struct MSF2State MSF2State;
#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
#define MSF2_NUM_SPIS 2
@ -44,7 +46,7 @@
*/
#define MSF2_NUM_TIMERS 2
typedef struct MSF2State {
struct MSF2State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -64,6 +66,6 @@ typedef struct MSF2State {
MSSTimerState timer;
MSSSpiState spi[MSF2_NUM_SPIS];
MSF2EmacState emac;
} MSF2State;
};
#endif

6
include/hw/arm/nrf51_soc.h
View file

@ -17,14 +17,16 @@
#include "hw/gpio/nrf51_gpio.h"
#include "hw/nvram/nrf51_nvm.h"
#include "hw/timer/nrf51_timer.h"
#include "qom/object.h"
#define TYPE_NRF51_SOC "nrf51-soc"
typedef struct NRF51State NRF51State;
#define NRF51_SOC(obj) \
OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC)
#define NRF51_NUM_TIMERS 3
typedef struct NRF51State {
struct NRF51State {
/*< private >*/
SysBusDevice parent_obj;
@ -50,6 +52,6 @@ typedef struct NRF51State {
MemoryRegion container;
} NRF51State;
};
#endif

5
include/hw/arm/omap.h
View file

@ -24,6 +24,7 @@
#include "hw/input/tsc2xxx.h"
#include "target/arm/cpu-qom.h"
#include "qemu/log.h"
#include "qom/object.h"
# define OMAP_EMIFS_BASE 0x00000000
# define OMAP2_Q0_BASE 0x00000000
@ -69,10 +70,10 @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
/* omap_intc.c */
#define TYPE_OMAP_INTC "common-omap-intc"
typedef struct omap_intr_handler_s omap_intr_handler;
#define OMAP_INTC(obj) \
OBJECT_CHECK(omap_intr_handler, (obj), TYPE_OMAP_INTC)
typedef struct omap_intr_handler_s omap_intr_handler;
/*
* TODO: Ideally we should have a clock framework that
@ -93,9 +94,9 @@ void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk);
/* omap_i2c.c */
#define TYPE_OMAP_I2C "omap_i2c"
typedef struct OMAPI2CState OMAPI2CState;
#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C)
typedef struct OMAPI2CState OMAPI2CState;
/* TODO: clock framework (see above) */
void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk);

1
include/hw/arm/pxa.h
View file

@ -13,6 +13,7 @@
#include "exec/memory.h"
#include "target/arm/cpu-qom.h"
#include "hw/pcmcia.h"
#include "qom/object.h"
/* Interrupt numbers */
# define PXA2XX_PIC_SSP3 0

11
include/hw/arm/smmu-common.h
View file

@ -21,6 +21,7 @@
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
#include "qom/object.h"
#define SMMU_PCI_BUS_MAX 256
#define SMMU_PCI_DEVFN_MAX 256
@ -102,7 +103,7 @@ typedef struct SMMUIOTLBKey {
uint8_t level;
} SMMUIOTLBKey;
typedef struct SMMUState {
struct SMMUState {
/* <private> */
SysBusDevice dev;
const char *mrtypename;
@ -116,9 +117,10 @@ typedef struct SMMUState {
QLIST_HEAD(, SMMUDevice) devices_with_notifiers;
uint8_t bus_num;
PCIBus *primary_bus;
} SMMUState;
};
typedef struct SMMUState SMMUState;
typedef struct {
struct SMMUBaseClass {
/* <private> */
SysBusDeviceClass parent_class;
@ -126,7 +128,8 @@ typedef struct {
DeviceRealize parent_realize;
} SMMUBaseClass;
};
typedef struct SMMUBaseClass SMMUBaseClass;
#define TYPE_ARM_SMMU "arm-smmu"
#define ARM_SMMU(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_ARM_SMMU)

11
include/hw/arm/smmuv3.h
View file

@ -21,6 +21,7 @@
#include "hw/arm/smmu-common.h"
#include "hw/registerfields.h"
#include "qom/object.h"
#define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
@ -32,7 +33,7 @@ typedef struct SMMUQueue {
uint8_t log2size;
} SMMUQueue;
typedef struct SMMUv3State {
struct SMMUv3State {
SMMUState smmu_state;
uint32_t features;
@ -61,7 +62,8 @@ typedef struct SMMUv3State {
qemu_irq irq[4];
QemuMutex mutex;
} SMMUv3State;
};
typedef struct SMMUv3State SMMUv3State;
typedef enum {
SMMU_IRQ_EVTQ,
@ -70,14 +72,15 @@ typedef enum {
SMMU_IRQ_GERROR,
} SMMUIrq;
typedef struct {
struct SMMUv3Class {
/*< private >*/
SMMUBaseClass smmu_base_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
} SMMUv3Class;
};
typedef struct SMMUv3Class SMMUv3Class;
#define TYPE_ARM_SMMUV3 "arm-smmuv3"
#define ARM_SMMUV3(obj) OBJECT_CHECK(SMMUv3State, (obj), TYPE_ARM_SMMUV3)

6
include/hw/arm/stm32f205_soc.h
View file

@ -32,8 +32,10 @@
#include "hw/or-irq.h"
#include "hw/ssi/stm32f2xx_spi.h"
#include "hw/arm/armv7m.h"
#include "qom/object.h"
#define TYPE_STM32F205_SOC "stm32f205-soc"
typedef struct STM32F205State STM32F205State;
#define STM32F205_SOC(obj) \
OBJECT_CHECK(STM32F205State, (obj), TYPE_STM32F205_SOC)
@ -47,7 +49,7 @@
#define SRAM_BASE_ADDRESS 0x20000000
#define SRAM_SIZE (128 * 1024)
typedef struct STM32F205State {
struct STM32F205State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -63,6 +65,6 @@ typedef struct STM32F205State {
STM32F2XXSPIState spi[STM_NUM_SPIS];
qemu_or_irq *adc_irqs;
} STM32F205State;
};
#endif

6
include/hw/arm/stm32f405_soc.h
View file

@ -33,8 +33,10 @@
#include "hw/or-irq.h"
#include "hw/ssi/stm32f2xx_spi.h"
#include "hw/arm/armv7m.h"
#include "qom/object.h"
#define TYPE_STM32F405_SOC "stm32f405-soc"
typedef struct STM32F405State STM32F405State;
#define STM32F405_SOC(obj) \
OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC)
@ -48,7 +50,7 @@
#define SRAM_BASE_ADDRESS 0x20000000
#define SRAM_SIZE (192 * 1024)
typedef struct STM32F405State {
struct STM32F405State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -68,6 +70,6 @@ typedef struct STM32F405State {
MemoryRegion sram;
MemoryRegion flash;
MemoryRegion flash_alias;
} STM32F405State;
};
#endif

11
include/hw/arm/virt.h
View file

@ -37,6 +37,7 @@
#include "hw/block/flash.h"
#include "sysemu/kvm.h"
#include "hw/intc/arm_gicv3_common.h"
#include "qom/object.h"
#define NUM_GICV2M_SPIS 64
#define NUM_VIRTIO_TRANSPORTS 32
@ -115,7 +116,7 @@ typedef struct MemMapEntry {
hwaddr size;
} MemMapEntry;
typedef struct {
struct VirtMachineClass {
MachineClass parent;
bool disallow_affinity_adjustment;
bool no_its;
@ -126,9 +127,10 @@ typedef struct {
bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */
bool kvm_no_adjvtime;
bool acpi_expose_flash;
} VirtMachineClass;
};
typedef struct VirtMachineClass VirtMachineClass;
typedef struct {
struct VirtMachineState {
MachineState parent;
Notifier machine_done;
DeviceState *platform_bus_dev;
@ -162,7 +164,8 @@ typedef struct {
DeviceState *gic;
DeviceState *acpi_dev;
Notifier powerdown_notifier;
} VirtMachineState;
};
typedef struct VirtMachineState VirtMachineState;
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)

6
include/hw/arm/xlnx-versal.h
View file

@ -20,8 +20,10 @@
#include "hw/dma/xlnx-zdma.h"
#include "hw/net/cadence_gem.h"
#include "hw/rtc/xlnx-zynqmp-rtc.h"
#include "qom/object.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
typedef struct Versal Versal;
#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
#define XLNX_VERSAL_NR_ACPUS 2
@ -31,7 +33,7 @@
#define XLNX_VERSAL_NR_SDS 2
#define XLNX_VERSAL_NR_IRQS 192
typedef struct Versal {
struct Versal {
/*< private >*/
SysBusDevice parent_obj;
@ -74,7 +76,7 @@ typedef struct Versal {
MemoryRegion *mr_ddr;
uint32_t psci_conduit;
} cfg;
} Versal;
};
/* Memory-map and IRQ definitions. Copied a subset from
* auto-generated files. */

6
include/hw/arm/xlnx-zynqmp.h
View file

@ -32,8 +32,10 @@
#include "hw/rtc/xlnx-zynqmp-rtc.h"
#include "hw/cpu/cluster.h"
#include "target/arm/cpu.h"
#include "qom/object.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
typedef struct XlnxZynqMPState XlnxZynqMPState;
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
TYPE_XLNX_ZYNQMP)
@ -73,7 +75,7 @@
#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
typedef struct XlnxZynqMPState {
struct XlnxZynqMPState {
/*< private >*/
DeviceState parent_obj;
@ -112,6 +114,6 @@ typedef struct XlnxZynqMPState {
bool virt;
/* Has the RPU subsystem? */
bool has_rpu;
} XlnxZynqMPState;
};
#endif

5
include/hw/block/flash.h
View file

@ -4,14 +4,15 @@
/* NOR flash devices */
#include "exec/hwaddr.h"
#include "qom/object.h"
/* pflash_cfi01.c */
#define TYPE_PFLASH_CFI01 "cfi.pflash01"
typedef struct PFlashCFI01 PFlashCFI01;
#define PFLASH_CFI01(obj) \
OBJECT_CHECK(PFlashCFI01, (obj), TYPE_PFLASH_CFI01)
typedef struct PFlashCFI01 PFlashCFI01;
PFlashCFI01 *pflash_cfi01_register(hwaddr base,
const char *name,
@ -29,10 +30,10 @@ void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo);
/* pflash_cfi02.c */
#define TYPE_PFLASH_CFI02 "cfi.pflash02"
typedef struct PFlashCFI02 PFlashCFI02;
#define PFLASH_CFI02(obj) \
OBJECT_CHECK(PFlashCFI02, (obj), TYPE_PFLASH_CFI02)
typedef struct PFlashCFI02 PFlashCFI02;
PFlashCFI02 *pflash_cfi02_register(hwaddr base,
const char *name,

6
include/hw/block/swim.h
View file

@ -13,6 +13,7 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "qom/object.h"
#define SWIM_MAX_FD 2
@ -67,10 +68,11 @@ struct SWIMCtrl {
};
#define TYPE_SWIM "swim"
typedef struct Swim Swim;
#define SWIM(obj) OBJECT_CHECK(Swim, (obj), TYPE_SWIM)
typedef struct Swim {
struct Swim {
SysBusDevice parent_obj;
SWIMCtrl ctrl;
} Swim;
};
#endif

6
include/hw/char/avr_usart.h
View file

@ -25,6 +25,7 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "hw/hw.h"
#include "qom/object.h"
/* Offsets of registers. */
#define USART_DR 0x06
@ -57,10 +58,11 @@
#define USART_CSRC_CSZ0 (1 << 1)
#define TYPE_AVR_USART "avr-usart"
typedef struct AVRUsartState AVRUsartState;
#define AVR_USART(obj) \
OBJECT_CHECK(AVRUsartState, (obj), TYPE_AVR_USART)
typedef struct {
struct AVRUsartState {
/* <private> */
SysBusDevice parent_obj;
@ -88,6 +90,6 @@ typedef struct {
qemu_irq txc_irq;
/* Data Register Empty */
qemu_irq dre_irq;
} AVRUsartState;
};
#endif /* HW_CHAR_AVR_USART_H */

6
include/hw/char/bcm2835_aux.h
View file

@ -11,13 +11,15 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
#define TYPE_BCM2835_AUX "bcm2835-aux"
typedef struct BCM2835AuxState BCM2835AuxState;
#define BCM2835_AUX(obj) OBJECT_CHECK(BCM2835AuxState, (obj), TYPE_BCM2835_AUX)
#define BCM2835_AUX_RX_FIFO_LEN 8
typedef struct {
struct BCM2835AuxState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -29,6 +31,6 @@ typedef struct {
uint8_t read_fifo[BCM2835_AUX_RX_FIFO_LEN];
uint8_t read_pos, read_count;
uint8_t ier, iir;
} BCM2835AuxState;
};
#endif

6
include/hw/char/cadence_uart.h
View file

@ -24,6 +24,7 @@
#include "chardev/char-fe.h"
#include "qapi/error.h"
#include "qemu/timer.h"
#include "qom/object.h"
#define CADENCE_UART_RX_FIFO_SIZE 16
#define CADENCE_UART_TX_FIFO_SIZE 16
@ -31,10 +32,11 @@
#define CADENCE_UART_R_MAX (0x48/4)
#define TYPE_CADENCE_UART "cadence_uart"
typedef struct CadenceUARTState CadenceUARTState;
#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
TYPE_CADENCE_UART)
typedef struct {
struct CadenceUARTState {
/*< private >*/
SysBusDevice parent_obj;
@ -51,6 +53,6 @@ typedef struct {
qemu_irq irq;
QEMUTimer *fifo_trigger_handle;
Clock *refclk;
} CadenceUARTState;
};
#endif

6
include/hw/char/cmsdk-apb-uart.h
View file

@ -15,12 +15,14 @@
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
#define TYPE_CMSDK_APB_UART "cmsdk-apb-uart"
typedef struct CMSDKAPBUART CMSDKAPBUART;
#define CMSDK_APB_UART(obj) OBJECT_CHECK(CMSDKAPBUART, (obj), \
TYPE_CMSDK_APB_UART)
typedef struct {
struct CMSDKAPBUART {
/*< private >*/
SysBusDevice parent_obj;
@ -42,7 +44,7 @@ typedef struct {
/* This UART has no FIFO, only a 1-character buffer for each of Tx and Rx */
uint8_t txbuf;
uint8_t rxbuf;
} CMSDKAPBUART;
};
/**
* cmsdk_apb_uart_create - convenience function to create TYPE_CMSDK_APB_UART

6
include/hw/char/digic-uart.h
View file

@ -20,8 +20,10 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
#define TYPE_DIGIC_UART "digic-uart"
typedef struct DigicUartState DigicUartState;
#define DIGIC_UART(obj) \
OBJECT_CHECK(DigicUartState, (obj), TYPE_DIGIC_UART)
@ -32,7 +34,7 @@ enum {
R_MAX
};
typedef struct DigicUartState {
struct DigicUartState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -42,6 +44,6 @@ typedef struct DigicUartState {
uint32_t reg_rx;
uint32_t reg_st;
} DigicUartState;
};
#endif /* HW_CHAR_DIGIC_UART_H */

6
include/hw/char/escc.h
View file

@ -5,11 +5,13 @@
#include "chardev/char-serial.h"
#include "hw/sysbus.h"
#include "ui/input.h"
#include "qom/object.h"
/* escc.c */
#define TYPE_ESCC "escc"
#define ESCC_SIZE 4
typedef struct ESCCState ESCCState;
#define ESCC(obj) OBJECT_CHECK(ESCCState, (obj), TYPE_ESCC)
typedef enum {
@ -46,7 +48,7 @@ typedef struct ESCCChannelState {
QemuInputHandlerState *hs;
} ESCCChannelState;
typedef struct ESCCState {
struct ESCCState {
SysBusDevice parent_obj;
struct ESCCChannelState chn[2];
@ -55,6 +57,6 @@ typedef struct ESCCState {
MemoryRegion mmio;
uint32_t disabled;
uint32_t frequency;
} ESCCState;
};
#endif

6
include/hw/char/ibex_uart.h
View file

@ -29,6 +29,7 @@
#include "hw/registerfields.h"
#include "chardev/char-fe.h"
#include "qemu/timer.h"
#include "qom/object.h"
REG32(INTR_STATE, 0x00)
FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
@ -69,10 +70,11 @@ REG32(TIMEOUT_CTRL, 0x2c)
#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
#define TYPE_IBEX_UART "ibex-uart"
typedef struct IbexUartState IbexUartState;
#define IBEX_UART(obj) \
OBJECT_CHECK(IbexUartState, (obj), TYPE_IBEX_UART)
typedef struct {
struct IbexUartState {
/* <private> */
SysBusDevice parent_obj;
@ -103,5 +105,5 @@ typedef struct {
qemu_irq rx_watermark;
qemu_irq tx_empty;
qemu_irq rx_overflow;
} IbexUartState;
};
#endif /* HW_IBEX_UART_H */

6
include/hw/char/imx_serial.h
View file

@ -20,8 +20,10 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
#define TYPE_IMX_SERIAL "imx.serial"
typedef struct IMXSerialState IMXSerialState;
#define IMX_SERIAL(obj) OBJECT_CHECK(IMXSerialState, (obj), TYPE_IMX_SERIAL)
#define URXD_CHARRDY (1<<15) /* character read is valid */
@ -76,7 +78,7 @@
#define UTS1_TXFULL (1<<4)
#define UTS1_RXFULL (1<<3)
typedef struct IMXSerialState {
struct IMXSerialState {
/*< private >*/
SysBusDevice parent_obj;
@ -103,6 +105,6 @@ typedef struct IMXSerialState {
qemu_irq irq;
CharBackend chr;
} IMXSerialState;
};
#endif

6
include/hw/char/nrf51_uart.h
View file

@ -14,11 +14,13 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "hw/registerfields.h"
#include "qom/object.h"
#define UART_FIFO_LENGTH 6
#define UART_SIZE 0x1000
#define TYPE_NRF51_UART "nrf51_soc.uart"
typedef struct NRF51UARTState NRF51UARTState;
#define NRF51_UART(obj) OBJECT_CHECK(NRF51UARTState, (obj), TYPE_NRF51_UART)
REG32(UART_STARTRX, 0x000)
@ -54,7 +56,7 @@ REG32(UART_TXD, 0x51C)
REG32(UART_BAUDRATE, 0x524)
REG32(UART_CONFIG, 0x56C)
typedef struct NRF51UARTState {
struct NRF51UARTState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -72,6 +74,6 @@ typedef struct NRF51UARTState {
bool tx_started;
bool pending_tx_byte;
bool enabled;
} NRF51UARTState;
};
#endif

6
include/hw/char/pl011.h
View file

@ -19,14 +19,16 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qapi/error.h"
#include "qom/object.h"
#define TYPE_PL011 "pl011"
typedef struct PL011State PL011State;
#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)
/* This shares the same struct (and cast macro) as the base pl011 device */
#define TYPE_PL011_LUMINARY "pl011_luminary"
typedef struct PL011State {
struct PL011State {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -49,7 +51,7 @@ typedef struct PL011State {
CharBackend chr;
qemu_irq irq[6];
const unsigned char *id;
} PL011State;
};
static inline DeviceState *pl011_create(hwaddr addr,
qemu_irq irq,

6
include/hw/char/renesas_sci.h
View file

@ -11,8 +11,10 @@
#include "chardev/char-fe.h"
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_RENESAS_SCI "renesas-sci"
typedef struct RSCIState RSCIState;
#define RSCI(obj) OBJECT_CHECK(RSCIState, (obj), TYPE_RENESAS_SCI)
enum {
@ -23,7 +25,7 @@ enum {
SCI_NR_IRQ = 4
};
typedef struct {
struct RSCIState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -46,6 +48,6 @@ typedef struct {
int64_t trtime;
int64_t rx_next;
uint64_t input_freq;
} RSCIState;
};
#endif

16
include/hw/char/serial.h
View file

@ -31,10 +31,11 @@
#include "qemu/fifo8.h"
#include "chardev/char.h"
#include "hw/sysbus.h"
#include "qom/object.h"
#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
typedef struct SerialState {
struct SerialState {
DeviceState parent;
uint16_t divider;
@ -77,22 +78,25 @@ typedef struct SerialState {
QEMUTimer *modem_status_poll;
MemoryRegion io;
} SerialState;
};
typedef struct SerialState SerialState;
typedef struct SerialMM {
struct SerialMM {
SysBusDevice parent;
SerialState serial;
uint8_t regshift;
uint8_t endianness;
} SerialMM;
};
typedef struct SerialMM SerialMM;
typedef struct SerialIO {
struct SerialIO {
SysBusDevice parent;
SerialState serial;
} SerialIO;
};
typedef struct SerialIO SerialIO;
extern const VMStateDescription vmstate_serial;
extern const MemoryRegionOps serial_io_ops;

6
include/hw/char/stm32f2xx_usart.h
View file

@ -27,6 +27,7 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
#define USART_SR 0x00
#define USART_DR 0x04
@ -53,10 +54,11 @@
#define USART_CR1_RE (1 << 2)
#define TYPE_STM32F2XX_USART "stm32f2xx-usart"
typedef struct STM32F2XXUsartState STM32F2XXUsartState;
#define STM32F2XX_USART(obj) \
OBJECT_CHECK(STM32F2XXUsartState, (obj), TYPE_STM32F2XX_USART)
typedef struct {
struct STM32F2XXUsartState {
/* <private> */
SysBusDevice parent_obj;
@ -73,5 +75,5 @@ typedef struct {
CharBackend chr;
qemu_irq irq;
} STM32F2XXUsartState;
};
#endif /* HW_STM32F2XX_USART_H */

2
include/hw/clock.h
View file

@ -18,6 +18,7 @@
#include "qemu/queue.h"
#define TYPE_CLOCK "clock"
typedef struct Clock Clock;
#define CLOCK(obj) OBJECT_CHECK(Clock, (obj), TYPE_CLOCK)
typedef void ClockCallback(void *opaque);
@ -54,7 +55,6 @@ typedef void ClockCallback(void *opaque);
* @sibling: structure used to form a clock list
*/
typedef struct Clock Clock;
struct Clock {
/*< private >*/

6
include/hw/core/cpu.h
View file

@ -30,6 +30,7 @@
#include "qemu/queue.h"
#include "qemu/thread.h"
#include "qemu/plugin.h"
#include "qom/object.h"
typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
void *opaque);
@ -61,6 +62,7 @@ typedef uint64_t vaddr;
*/
#define CPU(obj) ((CPUState *)(obj))
typedef struct CPUClass CPUClass;
#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
@ -156,7 +158,7 @@ struct TranslationBlock;
*
* Represents a CPU family or model.
*/
typedef struct CPUClass {
struct CPUClass {
/*< private >*/
DeviceClass parent_class;
/*< public >*/
@ -222,7 +224,7 @@ typedef struct CPUClass {
/* Keep non-pointer data at the end to minimize holes. */
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
} CPUClass;
};
/*
* Low 16 bits: number of cycles left, used only in icount mode.

6
include/hw/core/generic-loader.h
View file

@ -20,8 +20,9 @@
#include "elf.h"
#include "hw/qdev-core.h"
#include "qom/object.h"
typedef struct GenericLoaderState {
struct GenericLoaderState {
/* <private> */
DeviceState parent_obj;
@ -38,7 +39,8 @@ typedef struct GenericLoaderState {
bool force_raw;
bool data_be;
bool set_pc;
} GenericLoaderState;
};
typedef struct GenericLoaderState GenericLoaderState;
#define TYPE_GENERIC_LOADER "loader"
#define GENERIC_LOADER(obj) OBJECT_CHECK(GenericLoaderState, (obj), \

6
include/hw/cpu/a15mpcore.h
View file

@ -22,14 +22,16 @@
#include "hw/sysbus.h"
#include "hw/intc/arm_gic.h"
#include "qom/object.h"
/* A15MP private memory region. */
#define TYPE_A15MPCORE_PRIV "a15mpcore_priv"
typedef struct A15MPPrivState A15MPPrivState;
#define A15MPCORE_PRIV(obj) \
OBJECT_CHECK(A15MPPrivState, (obj), TYPE_A15MPCORE_PRIV)
typedef struct A15MPPrivState {
struct A15MPPrivState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -39,6 +41,6 @@ typedef struct A15MPPrivState {
MemoryRegion container;
GICState gic;
} A15MPPrivState;
};
#endif

6
include/hw/cpu/a9mpcore.h
View file

@ -15,12 +15,14 @@
#include "hw/misc/a9scu.h"
#include "hw/timer/arm_mptimer.h"
#include "hw/timer/a9gtimer.h"
#include "qom/object.h"
#define TYPE_A9MPCORE_PRIV "a9mpcore_priv"
typedef struct A9MPPrivState A9MPPrivState;
#define A9MPCORE_PRIV(obj) \
OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV)
typedef struct A9MPPrivState {
struct A9MPPrivState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -34,6 +36,6 @@ typedef struct A9MPPrivState {
A9GTimerState gtimer;
ARMMPTimerState mptimer;
ARMMPTimerState wdt;
} A9MPPrivState;
};
#endif

6
include/hw/cpu/arm11mpcore.h
View file

@ -14,12 +14,14 @@
#include "hw/misc/arm11scu.h"
#include "hw/intc/arm_gic.h"
#include "hw/timer/arm_mptimer.h"
#include "qom/object.h"
#define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv"
typedef struct ARM11MPCorePriveState ARM11MPCorePriveState;
#define ARM11MPCORE_PRIV(obj) \
OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV)
typedef struct ARM11MPCorePriveState {
struct ARM11MPCorePriveState {
SysBusDevice parent_obj;
uint32_t num_cpu;
@ -30,6 +32,6 @@ typedef struct ARM11MPCorePriveState {
GICState gic;
ARMMPTimerState mptimer;
ARMMPTimerState wdtimer;
} ARM11MPCorePriveState;
};
#endif

6
include/hw/cpu/cluster.h
View file

@ -21,6 +21,7 @@
#define HW_CPU_CLUSTER_H
#include "hw/qdev-core.h"
#include "qom/object.h"
/*
* CPU Cluster type
@ -54,6 +55,7 @@
*/
#define TYPE_CPU_CLUSTER "cpu-cluster"
typedef struct CPUClusterState CPUClusterState;
#define CPU_CLUSTER(obj) \
OBJECT_CHECK(CPUClusterState, (obj), TYPE_CPU_CLUSTER)
@ -70,12 +72,12 @@
*
* State of a CPU cluster.
*/
typedef struct CPUClusterState {
struct CPUClusterState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
uint32_t cluster_id;
} CPUClusterState;
};
#endif

6
include/hw/cpu/core.h
View file

@ -10,20 +10,22 @@
#define HW_CPU_CORE_H
#include "hw/qdev-core.h"
#include "qom/object.h"
#define TYPE_CPU_CORE "cpu-core"
typedef struct CPUCore CPUCore;
#define CPU_CORE(obj) \
OBJECT_CHECK(CPUCore, (obj), TYPE_CPU_CORE)
typedef struct CPUCore {
struct CPUCore {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
int core_id;
int nr_threads;
} CPUCore;
};
/* Note: topology field names need to be kept in sync with
* 'CpuInstanceProperties' */

6
include/hw/display/bcm2835_fb.h
View file

@ -14,8 +14,10 @@
#include "hw/sysbus.h"
#include "ui/console.h"
#include "qom/object.h"
#define TYPE_BCM2835_FB "bcm2835-fb"
typedef struct BCM2835FBState BCM2835FBState;
#define BCM2835_FB(obj) OBJECT_CHECK(BCM2835FBState, (obj), TYPE_BCM2835_FB)
/*
@ -32,7 +34,7 @@ typedef struct {
uint32_t alpha;
} BCM2835FBConfig;
typedef struct {
struct BCM2835FBState {
/*< private >*/
SysBusDevice busdev;
/*< public >*/
@ -49,7 +51,7 @@ typedef struct {
BCM2835FBConfig config;
BCM2835FBConfig initial_config;
} BCM2835FBState;
};
void bcm2835_fb_reconfigure(BCM2835FBState *s, BCM2835FBConfig *newconfig);

1
include/hw/display/dpcd.h
View file

@ -24,6 +24,7 @@
#ifndef DPCD_H
#define DPCD_H
#include "qom/object.h"
typedef struct DPCDState DPCDState;

1
include/hw/display/i2c-ddc.h
View file

@ -21,6 +21,7 @@
#include "hw/display/edid.h"
#include "hw/i2c/i2c.h"
#include "qom/object.h"
/* A simple I2C slave which just returns the contents of its EDID blob. */
struct I2CDDCState {

18
include/hw/display/macfb.h
View file

@ -16,6 +16,7 @@
#include "qemu/osdep.h"
#include "exec/memory.h"
#include "ui/console.h"
#include "qom/object.h"
typedef struct MacfbState {
MemoryRegion mem_vram;
@ -31,34 +32,37 @@ typedef struct MacfbState {
} MacfbState;
#define TYPE_MACFB "sysbus-macfb"
typedef struct MacfbSysBusState MacfbSysBusState;
#define MACFB(obj) \
OBJECT_CHECK(MacfbSysBusState, (obj), TYPE_MACFB)
typedef struct {
struct MacfbSysBusState {
SysBusDevice busdev;
MacfbState macfb;
} MacfbSysBusState;
};
#define TYPE_NUBUS_MACFB "nubus-macfb"
typedef struct MacfbNubusDeviceClass MacfbNubusDeviceClass;
typedef struct MacfbNubusState MacfbNubusState;
#define NUBUS_MACFB_CLASS(class) \
OBJECT_CLASS_CHECK(MacfbNubusDeviceClass, (class), TYPE_NUBUS_MACFB)
#define NUBUS_MACFB_GET_CLASS(obj) \
OBJECT_GET_CLASS(MacfbNubusDeviceClass, (obj), TYPE_NUBUS_MACFB)
typedef struct MacfbNubusDeviceClass {
struct MacfbNubusDeviceClass {
DeviceClass parent_class;
DeviceRealize parent_realize;
} MacfbNubusDeviceClass;
};
#define TYPE_NUBUS_MACFB "nubus-macfb"
#define NUBUS_MACFB(obj) \
OBJECT_CHECK(MacfbNubusState, (obj), TYPE_NUBUS_MACFB)
typedef struct {
struct MacfbNubusState {
NubusDevice busdev;
MacfbState macfb;
} MacfbNubusState;
};
#endif

6
include/hw/display/xlnx_dp.h
View file

@ -34,6 +34,7 @@
#include "qemu/units.h"
#include "hw/dma/xlnx_dpdma.h"
#include "audio/audio.h"
#include "qom/object.h"
#define AUD_CHBUF_MAX_DEPTH (32 * KiB)
#define MAX_QEMU_BUFFER_SIZE (4 * KiB)
@ -48,7 +49,7 @@ struct PixmanPlane {
DisplaySurface *surface;
};
typedef struct XlnxDPState {
struct XlnxDPState {
/*< private >*/
SysBusDevice parent_obj;
@ -101,7 +102,8 @@ typedef struct XlnxDPState {
*/
DPCDState *dpcd;
I2CDDCState *edid;
} XlnxDPState;
};
typedef struct XlnxDPState XlnxDPState;
#define TYPE_XLNX_DP "xlnx.v-dp"
#define XLNX_DP(obj) OBJECT_CHECK(XlnxDPState, (obj), TYPE_XLNX_DP)

6
include/hw/dma/bcm2835_dma.h
View file

@ -9,6 +9,7 @@
#define BCM2835_DMA_H
#include "hw/sysbus.h"
#include "qom/object.h"
typedef struct {
uint32_t cs;
@ -25,12 +26,13 @@ typedef struct {
} BCM2835DMAChan;
#define TYPE_BCM2835_DMA "bcm2835-dma"
typedef struct BCM2835DMAState BCM2835DMAState;
#define BCM2835_DMA(obj) \
OBJECT_CHECK(BCM2835DMAState, (obj), TYPE_BCM2835_DMA)
#define BCM2835_DMA_NCHANS 16
typedef struct {
struct BCM2835DMAState {
/*< private >*/
SysBusDevice busdev;
/*< public >*/
@ -42,6 +44,6 @@ typedef struct {
BCM2835DMAChan chan[BCM2835_DMA_NCHANS];
uint32_t int_status;
uint32_t enable;
} BCM2835DMAState;
};
#endif

6
include/hw/dma/i8257.h
View file

@ -3,8 +3,10 @@
#include "hw/isa/isa.h"
#include "exec/ioport.h"
#include "qom/object.h"
#define TYPE_I8257 "i8257"
typedef struct I8257State I8257State;
#define I8257(obj) \
OBJECT_CHECK(I8257State, (obj), TYPE_I8257)
@ -20,7 +22,7 @@ typedef struct I8257Regs {
void *opaque;
} I8257Regs;
typedef struct I8257State {
struct I8257State {
/* <private> */
ISADevice parent_obj;
@ -43,7 +45,7 @@ typedef struct I8257State {
int running;
PortioList portio_page;
PortioList portio_pageh;
} I8257State;
};
void i8257_dma_init(ISABus *bus, bool high_page_enable);

6
include/hw/dma/pl080.h
View file

@ -29,6 +29,7 @@
#define HW_DMA_PL080_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define PL080_MAX_CHANNELS 8
@ -42,9 +43,10 @@ typedef struct {
#define TYPE_PL080 "pl080"
#define TYPE_PL081 "pl081"
typedef struct PL080State PL080State;
#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)
typedef struct PL080State {
struct PL080State {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -66,6 +68,6 @@ typedef struct PL080State {
MemoryRegion *downstream;
AddressSpace downstream_as;
} PL080State;
};
#endif

6
include/hw/dma/xlnx-zdma.h
View file

@ -32,6 +32,7 @@
#include "hw/sysbus.h"
#include "hw/register.h"
#include "sysemu/dma.h"
#include "qom/object.h"
#define ZDMA_R_MAX (0x204 / 4)
@ -50,7 +51,7 @@ typedef union {
uint32_t words[4];
} XlnxZDMADescr;
typedef struct XlnxZDMA {
struct XlnxZDMA {
SysBusDevice parent_obj;
MemoryRegion iomem;
MemTxAttrs attr;
@ -74,7 +75,8 @@ typedef struct XlnxZDMA {
/* We don't model the common bufs. Must be at least 16 bytes
to model write only mode. */
uint8_t buf[2048];
} XlnxZDMA;
};
typedef struct XlnxZDMA XlnxZDMA;
#define TYPE_XLNX_ZDMA "xlnx.zdma"

6
include/hw/dma/xlnx-zynq-devcfg.h
View file

@ -29,9 +29,11 @@
#include "hw/register.h"
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_XLNX_ZYNQ_DEVCFG "xlnx.ps7-dev-cfg"
typedef struct XlnxZynqDevcfg XlnxZynqDevcfg;
#define XLNX_ZYNQ_DEVCFG(obj) \
OBJECT_CHECK(XlnxZynqDevcfg, (obj), TYPE_XLNX_ZYNQ_DEVCFG)
@ -46,7 +48,7 @@ typedef struct XlnxZynqDevcfgDMACmd {
uint32_t dest_len;
} XlnxZynqDevcfgDMACmd;
typedef struct XlnxZynqDevcfg {
struct XlnxZynqDevcfg {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -57,6 +59,6 @@ typedef struct XlnxZynqDevcfg {
uint32_t regs[XLNX_ZYNQ_DEVCFG_R_MAX];
RegisterInfo regs_info[XLNX_ZYNQ_DEVCFG_R_MAX];
} XlnxZynqDevcfg;
};
#endif

1
include/hw/dma/xlnx_dpdma.h
View file

@ -28,6 +28,7 @@
#include "hw/sysbus.h"
#include "ui/console.h"
#include "sysemu/dma.h"
#include "qom/object.h"
#define XLNX_DPDMA_REG_ARRAY_SIZE (0x1000 >> 2)

5
include/hw/fw-path-provider.h
View file

@ -22,6 +22,7 @@
#define TYPE_FW_PATH_PROVIDER "fw-path-provider"
typedef struct FWPathProviderClass FWPathProviderClass;
#define FW_PATH_PROVIDER_CLASS(klass) \
OBJECT_CLASS_CHECK(FWPathProviderClass, (klass), TYPE_FW_PATH_PROVIDER)
#define FW_PATH_PROVIDER_GET_CLASS(obj) \
@ -31,11 +32,11 @@
typedef struct FWPathProvider FWPathProvider;
typedef struct FWPathProviderClass {
struct FWPathProviderClass {
InterfaceClass parent_class;
char *(*get_dev_path)(FWPathProvider *p, BusState *bus, DeviceState *dev);
} FWPathProviderClass;
};
char *fw_path_provider_get_dev_path(FWPathProvider *p, BusState *bus,
DeviceState *dev);

11
include/hw/gpio/aspeed_gpio.h
View file

@ -11,8 +11,11 @@
#define ASPEED_GPIO_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_ASPEED_GPIO "aspeed.gpio"
typedef struct AspeedGPIOClass AspeedGPIOClass;
typedef struct AspeedGPIOState AspeedGPIOState;
#define ASPEED_GPIO(obj) OBJECT_CHECK(AspeedGPIOState, (obj), TYPE_ASPEED_GPIO)
#define ASPEED_GPIO_CLASS(klass) \
OBJECT_CLASS_CHECK(AspeedGPIOClass, (klass), TYPE_ASPEED_GPIO)
@ -58,16 +61,16 @@ typedef struct AspeedGPIOReg {
enum GPIORegType type;
} AspeedGPIOReg;
typedef struct AspeedGPIOClass {
struct AspeedGPIOClass {
SysBusDevice parent_obj;
const GPIOSetProperties *props;
uint32_t nr_gpio_pins;
uint32_t nr_gpio_sets;
uint32_t gap;
const AspeedGPIOReg *reg_table;
} AspeedGPIOClass;
};
typedef struct AspeedGPIOState {
struct AspeedGPIOState {
/* <private> */
SysBusDevice parent;
@ -95,6 +98,6 @@ typedef struct AspeedGPIOState {
uint32_t debounce_2;
uint32_t input_mask;
} sets[ASPEED_GPIO_MAX_NR_SETS];
} AspeedGPIOState;
};
#endif /* _ASPEED_GPIO_H_ */

6
include/hw/gpio/bcm2835_gpio.h
View file

@ -16,8 +16,9 @@
#include "hw/sd/sd.h"
#include "hw/sysbus.h"
#include "qom/object.h"
typedef struct BCM2835GpioState {
struct BCM2835GpioState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -31,7 +32,8 @@ typedef struct BCM2835GpioState {
uint32_t lev0, lev1;
uint8_t sd_fsel;
qemu_irq out[54];
} BCM2835GpioState;
};
typedef struct BCM2835GpioState BCM2835GpioState;
#define TYPE_BCM2835_GPIO "bcm2835_gpio"
#define BCM2835_GPIO(obj) \

6
include/hw/gpio/imx_gpio.h
View file

@ -21,8 +21,10 @@
#define IMX_GPIO_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_IMX_GPIO "imx.gpio"
typedef struct IMXGPIOState IMXGPIOState;
#define IMX_GPIO(obj) OBJECT_CHECK(IMXGPIOState, (obj), TYPE_IMX_GPIO)
#define IMX_GPIO_MEM_SIZE 0x20
@ -39,7 +41,7 @@
#define IMX_GPIO_PIN_COUNT 32
typedef struct IMXGPIOState {
struct IMXGPIOState {
/*< private >*/
SysBusDevice parent_obj;
@ -58,6 +60,6 @@ typedef struct IMXGPIOState {
qemu_irq irq[2];
qemu_irq output[IMX_GPIO_PIN_COUNT];
} IMXGPIOState;
};
#endif /* IMX_GPIO_H */

6
include/hw/gpio/nrf51_gpio.h
View file

@ -27,7 +27,9 @@
#define NRF51_GPIO_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_NRF51_GPIO "nrf51_soc.gpio"
typedef struct NRF51GPIOState NRF51GPIOState;
#define NRF51_GPIO(obj) OBJECT_CHECK(NRF51GPIOState, (obj), TYPE_NRF51_GPIO)
#define NRF51_GPIO_PINS 32
@ -47,7 +49,7 @@
#define NRF51_GPIO_PULLDOWN 1
#define NRF51_GPIO_PULLUP 3
typedef struct NRF51GPIOState {
struct NRF51GPIOState {
SysBusDevice parent_obj;
MemoryRegion mmio;
@ -63,7 +65,7 @@ typedef struct NRF51GPIOState {
uint32_t old_out_connected;
qemu_irq output[NRF51_GPIO_PINS];
} NRF51GPIOState;
};
#endif

5
include/hw/hotplug.h
View file

@ -16,6 +16,7 @@
#define TYPE_HOTPLUG_HANDLER "hotplug-handler"
typedef struct HotplugHandlerClass HotplugHandlerClass;
#define HOTPLUG_HANDLER_CLASS(klass) \
OBJECT_CLASS_CHECK(HotplugHandlerClass, (klass), TYPE_HOTPLUG_HANDLER)
#define HOTPLUG_HANDLER_GET_CLASS(obj) \
@ -50,7 +51,7 @@ typedef void (*hotplug_fn)(HotplugHandler *plug_handler,
* Used for device removal with devices that implement
* asynchronous and synchronous (surprise) removal.
*/
typedef struct HotplugHandlerClass {
struct HotplugHandlerClass {
/* <private> */
InterfaceClass parent;
@ -59,7 +60,7 @@ typedef struct HotplugHandlerClass {
hotplug_fn plug;
hotplug_fn unplug_request;
hotplug_fn unplug;
} HotplugHandlerClass;
};
/**
* hotplug_handler_plug:

6
include/hw/hyperv/vmbus-bridge.h
View file

@ -12,16 +12,18 @@
#include "hw/sysbus.h"
#include "hw/hyperv/vmbus.h"
#include "qom/object.h"
#define TYPE_VMBUS_BRIDGE "vmbus-bridge"
typedef struct VMBusBridge {
struct VMBusBridge {
SysBusDevice parent_obj;
uint8_t irq;
VMBus *bus;
} VMBusBridge;
};
typedef struct VMBusBridge VMBusBridge;
#define VMBUS_BRIDGE(obj) OBJECT_CHECK(VMBusBridge, (obj), TYPE_VMBUS_BRIDGE)

8
include/hw/hyperv/vmbus.h
View file

@ -16,9 +16,12 @@
#include "migration/vmstate.h"
#include "hw/hyperv/vmbus-proto.h"
#include "qemu/uuid.h"
#include "qom/object.h"
#define TYPE_VMBUS_DEVICE "vmbus-dev"
typedef struct VMBusDevice VMBusDevice;
typedef struct VMBusDeviceClass VMBusDeviceClass;
#define VMBUS_DEVICE(obj) \
OBJECT_CHECK(VMBusDevice, (obj), TYPE_VMBUS_DEVICE)
#define VMBUS_DEVICE_CLASS(klass) \
@ -44,11 +47,10 @@ typedef struct VMBusChannel VMBusChannel;
* Base class for VMBus devices. Includes one or more channels. Identified by
* class GUID and instance GUID.
*/
typedef struct VMBusDevice VMBusDevice;
typedef void(*VMBusChannelNotifyCb)(struct VMBusChannel *chan);
typedef struct VMBusDeviceClass {
struct VMBusDeviceClass {
DeviceClass parent;
QemuUUID classid;
@ -80,7 +82,7 @@ typedef struct VMBusDeviceClass {
* side, when there's work to do with the data in the channel ring buffers.
*/
VMBusChannelNotifyCb chan_notify_cb;
} VMBusDeviceClass;
};
struct VMBusDevice {
DeviceState parent;

6
include/hw/i2c/arm_sbcon_i2c.h
View file

@ -14,14 +14,16 @@
#include "hw/sysbus.h"
#include "hw/i2c/bitbang_i2c.h"
#include "qom/object.h"
#define TYPE_VERSATILE_I2C "versatile_i2c"
#define TYPE_ARM_SBCON_I2C TYPE_VERSATILE_I2C
typedef struct ArmSbconI2CState ArmSbconI2CState;
#define ARM_SBCON_I2C(obj) \
OBJECT_CHECK(ArmSbconI2CState, (obj), TYPE_ARM_SBCON_I2C)
typedef struct ArmSbconI2CState {
struct ArmSbconI2CState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -30,6 +32,6 @@ typedef struct ArmSbconI2CState {
bitbang_i2c_interface bitbang;
int out;
int in;
} ArmSbconI2CState;
};
#endif /* HW_I2C_ARM_SBCON_H */

11
include/hw/i2c/aspeed_i2c.h
View file

@ -23,11 +23,14 @@
#include "hw/i2c/i2c.h"
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_ASPEED_I2C "aspeed.i2c"
#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
#define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
typedef struct AspeedI2CClass AspeedI2CClass;
typedef struct AspeedI2CState AspeedI2CState;
#define ASPEED_I2C(obj) \
OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C)
@ -56,7 +59,7 @@ typedef struct AspeedI2CBus {
uint32_t dma_len;
} AspeedI2CBus;
typedef struct AspeedI2CState {
struct AspeedI2CState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -70,14 +73,14 @@ typedef struct AspeedI2CState {
AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES];
MemoryRegion *dram_mr;
AddressSpace dram_as;
} AspeedI2CState;
};
#define ASPEED_I2C_CLASS(klass) \
OBJECT_CLASS_CHECK(AspeedI2CClass, (klass), TYPE_ASPEED_I2C)
#define ASPEED_I2C_GET_CLASS(obj) \
OBJECT_GET_CLASS(AspeedI2CClass, (obj), TYPE_ASPEED_I2C)
typedef struct AspeedI2CClass {
struct AspeedI2CClass {
SysBusDeviceClass parent_class;
uint8_t num_busses;
@ -91,7 +94,7 @@ typedef struct AspeedI2CClass {
bool check_sram;
bool has_dma;
} AspeedI2CClass;
};
I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr);

6
include/hw/i2c/i2c.h
View file

@ -2,6 +2,7 @@
#define QEMU_I2C_H
#include "hw/qdev-core.h"
#include "qom/object.h"
/* The QEMU I2C implementation only supports simple transfers that complete
immediately. It does not support slave devices that need to be able to
@ -18,6 +19,7 @@ enum i2c_event {
typedef struct I2CSlave I2CSlave;
#define TYPE_I2C_SLAVE "i2c-slave"
typedef struct I2CSlaveClass I2CSlaveClass;
#define I2C_SLAVE(obj) \
OBJECT_CHECK(I2CSlave, (obj), TYPE_I2C_SLAVE)
#define I2C_SLAVE_CLASS(klass) \
@ -25,7 +27,7 @@ typedef struct I2CSlave I2CSlave;
#define I2C_SLAVE_GET_CLASS(obj) \
OBJECT_GET_CLASS(I2CSlaveClass, (obj), TYPE_I2C_SLAVE)
typedef struct I2CSlaveClass {
struct I2CSlaveClass {
DeviceClass parent_class;
/* Master to slave. Returns non-zero for a NAK, 0 for success. */
@ -43,7 +45,7 @@ typedef struct I2CSlaveClass {
* return code is not used and should be zero.
*/
int (*event)(I2CSlave *s, enum i2c_event event);
} I2CSlaveClass;
};
struct I2CSlave {
DeviceState qdev;

6
include/hw/i2c/imx_i2c.h
View file

@ -22,8 +22,10 @@
#define IMX_I2C_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_IMX_I2C "imx.i2c"
typedef struct IMXI2CState IMXI2CState;
#define IMX_I2C(obj) OBJECT_CHECK(IMXI2CState, (obj), TYPE_IMX_I2C)
#define IMX_I2C_MEM_SIZE 0x14
@ -65,7 +67,7 @@
#define ADDR_RESET 0xFF00
typedef struct IMXI2CState {
struct IMXI2CState {
/*< private >*/
SysBusDevice parent_obj;
@ -82,6 +84,6 @@ typedef struct IMXI2CState {
uint16_t i2sr;
uint16_t i2dr_read;
uint16_t i2dr_write;
} IMXI2CState;
};
#endif /* IMX_I2C_H */

6
include/hw/i2c/microbit_i2c.h
View file

@ -13,6 +13,7 @@
#include "hw/sysbus.h"
#include "hw/arm/nrf51.h"
#include "qom/object.h"
#define NRF51_TWI_TASK_STARTRX 0x000
#define NRF51_TWI_TASK_STARTTX 0x008
@ -26,17 +27,18 @@
#define NRF51_TWI_REG_ADDRESS 0x588
#define TYPE_MICROBIT_I2C "microbit.i2c"
typedef struct MicrobitI2CState MicrobitI2CState;
#define MICROBIT_I2C(obj) \
OBJECT_CHECK(MicrobitI2CState, (obj), TYPE_MICROBIT_I2C)
#define MICROBIT_I2C_NREGS (NRF51_PERIPHERAL_SIZE / sizeof(uint32_t))
typedef struct {
struct MicrobitI2CState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t regs[MICROBIT_I2C_NREGS];
uint32_t read_idx;
} MicrobitI2CState;
};
#endif /* MICROBIT_I2C_H */

6
include/hw/i2c/ppc4xx_i2c.h
View file

@ -29,11 +29,13 @@
#include "hw/sysbus.h"
#include "hw/i2c/bitbang_i2c.h"
#include "qom/object.h"
#define TYPE_PPC4xx_I2C "ppc4xx-i2c"
typedef struct PPC4xxI2CState PPC4xxI2CState;
#define PPC4xx_I2C(obj) OBJECT_CHECK(PPC4xxI2CState, (obj), TYPE_PPC4xx_I2C)
typedef struct PPC4xxI2CState {
struct PPC4xxI2CState {
/*< private >*/
SysBusDevice parent_obj;
@ -57,6 +59,6 @@ typedef struct PPC4xxI2CState {
uint8_t xfrcnt;
uint8_t xtcntlss;
uint8_t directcntl;
} PPC4xxI2CState;
};
#endif /* PPC4XX_I2C_H */

9
include/hw/i2c/smbus_slave.h
View file

@ -26,8 +26,11 @@
#define HW_SMBUS_SLAVE_H
#include "hw/i2c/i2c.h"
#include "qom/object.h"
#define TYPE_SMBUS_DEVICE "smbus-device"
typedef struct SMBusDevice SMBusDevice;
typedef struct SMBusDeviceClass SMBusDeviceClass;
#define SMBUS_DEVICE(obj) \
OBJECT_CHECK(SMBusDevice, (obj), TYPE_SMBUS_DEVICE)
#define SMBUS_DEVICE_CLASS(klass) \
@ -35,10 +38,8 @@
#define SMBUS_DEVICE_GET_CLASS(obj) \
OBJECT_GET_CLASS(SMBusDeviceClass, (obj), TYPE_SMBUS_DEVICE)
typedef struct SMBusDevice SMBusDevice;
typedef struct SMBusDeviceClass
{
struct SMBusDeviceClass {
I2CSlaveClass parent_class;
/*
@ -67,7 +68,7 @@ typedef struct SMBusDeviceClass
* return 0xff in that case.
*/
uint8_t (*receive_byte)(SMBusDevice *dev);
} SMBusDeviceClass;
};
#define SMBUS_DATA_MAX_LEN 34 /* command + len + 32 bytes of data. */

7
include/hw/i386/apic_internal.h
View file

@ -25,6 +25,7 @@
#include "exec/memory.h"
#include "qemu/timer.h"
#include "target/i386/cpu-qom.h"
#include "qom/object.h"
/* APIC Local Vector Table */
#define APIC_LVT_TIMER 0
@ -125,6 +126,7 @@
typedef struct APICCommonState APICCommonState;
#define TYPE_APIC_COMMON "apic-common"
typedef struct APICCommonClass APICCommonClass;
#define APIC_COMMON(obj) \
OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC_COMMON)
#define APIC_COMMON_CLASS(klass) \
@ -132,8 +134,7 @@ typedef struct APICCommonState APICCommonState;
#define APIC_COMMON_GET_CLASS(obj) \
OBJECT_GET_CLASS(APICCommonClass, (obj), TYPE_APIC_COMMON)
typedef struct APICCommonClass
{
struct APICCommonClass {
DeviceClass parent_class;
DeviceRealize realize;
@ -151,7 +152,7 @@ typedef struct APICCommonClass
* device, but it's convenient to have it here for now.
*/
void (*send_msi)(MSIMessage *msi);
} APICCommonClass;
};
struct APICCommonState {
/*< private >*/

6
include/hw/i386/ich9.h
View file

@ -11,6 +11,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
#include "hw/pci/pci_bus.h"
#include "qom/object.h"
void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
@ -23,10 +24,11 @@ void ich9_generate_smi(void);
#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
typedef struct ICH9LPCState ICH9LPCState;
#define ICH9_LPC_DEVICE(obj) \
OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
typedef struct ICH9LPCState {
struct ICH9LPCState {
/* ICH9 LPC PCI to ISA bridge */
PCIDevice d;
@ -77,7 +79,7 @@ typedef struct ICH9LPCState {
Notifier machine_ready;
qemu_irq gsi[GSI_NUM_PINS];
} ICH9LPCState;
};
#define Q35_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))

3
include/hw/i386/intel_iommu.h
View file

@ -24,8 +24,10 @@
#include "hw/i386/x86-iommu.h"
#include "qemu/iova-tree.h"
#include "qom/object.h"
#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
typedef struct IntelIOMMUState IntelIOMMUState;
#define INTEL_IOMMU_DEVICE(obj) \
OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
@ -56,7 +58,6 @@
typedef struct VTDContextEntry VTDContextEntry;
typedef struct VTDContextCacheEntry VTDContextCacheEntry;
typedef struct IntelIOMMUState IntelIOMMUState;
typedef struct VTDAddressSpace VTDAddressSpace;
typedef struct VTDIOTLBEntry VTDIOTLBEntry;
typedef struct VTDBus VTDBus;

6
include/hw/i386/ioapic_internal.h
View file

@ -25,6 +25,7 @@
#include "exec/memory.h"
#include "hw/sysbus.h"
#include "qemu/notify.h"
#include "qom/object.h"
#define MAX_IOAPICS 1
@ -84,6 +85,7 @@
typedef struct IOAPICCommonState IOAPICCommonState;
#define TYPE_IOAPIC_COMMON "ioapic-common"
typedef struct IOAPICCommonClass IOAPICCommonClass;
#define IOAPIC_COMMON(obj) \
OBJECT_CHECK(IOAPICCommonState, (obj), TYPE_IOAPIC_COMMON)
#define IOAPIC_COMMON_CLASS(klass) \
@ -91,14 +93,14 @@ typedef struct IOAPICCommonState IOAPICCommonState;
#define IOAPIC_COMMON_GET_CLASS(obj) \
OBJECT_GET_CLASS(IOAPICCommonClass, (obj), TYPE_IOAPIC_COMMON)
typedef struct IOAPICCommonClass {
struct IOAPICCommonClass {
SysBusDeviceClass parent_class;
DeviceRealize realize;
DeviceUnrealize unrealize;
void (*pre_save)(IOAPICCommonState *s);
void (*post_load)(IOAPICCommonState *s);
} IOAPICCommonClass;
};
struct IOAPICCommonState {
SysBusDevice busdev;

11
include/hw/i386/microvm.h
View file

@ -24,6 +24,7 @@
#include "hw/boards.h"
#include "hw/i386/x86.h"
#include "qom/object.h"
/* Platform virtio definitions */
#define VIRTIO_MMIO_BASE 0xfeb00000
@ -39,13 +40,14 @@
#define MICROVM_MACHINE_OPTION_ROMS "x-option-roms"
#define MICROVM_MACHINE_AUTO_KERNEL_CMDLINE "auto-kernel-cmdline"
typedef struct {
struct MicrovmMachineClass {
X86MachineClass parent;
HotplugHandler *(*orig_hotplug_handler)(MachineState *machine,
DeviceState *dev);
} MicrovmMachineClass;
};
typedef struct MicrovmMachineClass MicrovmMachineClass;
typedef struct {
struct MicrovmMachineState {
X86MachineState parent;
/* Machine type options */
@ -58,7 +60,8 @@ typedef struct {
/* Machine state */
bool kernel_cmdline_fixed;
} MicrovmMachineState;
};
typedef struct MicrovmMachineState MicrovmMachineState;
#define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm")
#define MICROVM_MACHINE(obj) \

6
include/hw/i386/pc.h
View file

@ -10,6 +10,7 @@
#include "hw/acpi/acpi_dev_interface.h"
#include "hw/hotplug.h"
#include "qom/object.h"
#define HPET_INTCAP "hpet-intcap"
@ -76,7 +77,7 @@ struct PCMachineState {
* way we can use 1GByte pages in the host.
*
*/
typedef struct PCMachineClass {
struct PCMachineClass {
/*< private >*/
X86MachineClass parent_class;
@ -118,7 +119,8 @@ typedef struct PCMachineClass {
/* use PVH to load kernels that support this feature */
bool pvh_enabled;
} PCMachineClass;
};
typedef struct PCMachineClass PCMachineClass;
#define TYPE_PC_MACHINE "generic-pc-machine"
#define PC_MACHINE(obj) \

5
include/hw/i386/x86-iommu.h
View file

@ -23,8 +23,11 @@
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
#include "hw/pci/msi.h"
#include "qom/object.h"
#define TYPE_X86_IOMMU_DEVICE ("x86-iommu")
typedef struct X86IOMMUClass X86IOMMUClass;
typedef struct X86IOMMUState X86IOMMUState;
#define X86_IOMMU_DEVICE(obj) \
OBJECT_CHECK(X86IOMMUState, (obj), TYPE_X86_IOMMU_DEVICE)
#define X86_IOMMU_DEVICE_CLASS(klass) \
@ -34,8 +37,6 @@
#define X86_IOMMU_SID_INVALID (0xffff)
typedef struct X86IOMMUState X86IOMMUState;
typedef struct X86IOMMUClass X86IOMMUClass;
typedef struct X86IOMMUIrq X86IOMMUIrq;
typedef struct X86IOMMU_MSIMessage X86IOMMU_MSIMessage;

11
include/hw/i386/x86.h
View file

@ -26,8 +26,9 @@
#include "hw/nmi.h"
#include "hw/isa/isa.h"
#include "hw/i386/ioapic.h"
#include "qom/object.h"
typedef struct {
struct X86MachineClass {
/*< private >*/
MachineClass parent;
@ -37,9 +38,10 @@ typedef struct {
bool save_tsc_khz;
/* Enables contiguous-apic-ID mode */
bool compat_apic_id_mode;
} X86MachineClass;
};
typedef struct X86MachineClass X86MachineClass;
typedef struct {
struct X86MachineState {
/*< private >*/
MachineState parent;
@ -68,7 +70,8 @@ typedef struct {
* will be translated to MSI messages in the address space.
*/
AddressSpace *ioapic_as;
} X86MachineState;
};
typedef struct X86MachineState X86MachineState;
#define X86_MACHINE_SMM "smm"
#define X86_MACHINE_ACPI "acpi"

11
include/hw/ide/ahci.h
View file

@ -25,6 +25,7 @@
#define HW_IDE_AHCI_H
#include "hw/sysbus.h"
#include "qom/object.h"
typedef struct AHCIDevice AHCIDevice;
@ -60,31 +61,33 @@ int32_t ahci_get_num_ports(PCIDevice *dev);
void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
#define TYPE_SYSBUS_AHCI "sysbus-ahci"
typedef struct SysbusAHCIState SysbusAHCIState;
#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
typedef struct SysbusAHCIState {
struct SysbusAHCIState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
AHCIState ahci;
uint32_t num_ports;
} SysbusAHCIState;
};
#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
typedef struct AllwinnerAHCIState AllwinnerAHCIState;
#define ALLWINNER_AHCI(obj) \
OBJECT_CHECK(AllwinnerAHCIState, (obj), TYPE_ALLWINNER_AHCI)
#define ALLWINNER_AHCI_MMIO_OFF 0x80
#define ALLWINNER_AHCI_MMIO_SIZE 0x80
typedef struct AllwinnerAHCIState {
struct AllwinnerAHCIState {
/*< private >*/
SysbusAHCIState parent_obj;
/*< public >*/
MemoryRegion mmio;
uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE/4];
} AllwinnerAHCIState;
};
#endif /* HW_IDE_AHCI_H */

6
include/hw/ide/internal.h
View file

@ -17,6 +17,7 @@
/* debug IDE devices */
#define USE_DMA_CDROM
#include "qom/object.h"
typedef struct IDEBus IDEBus;
typedef struct IDEDevice IDEDevice;
@ -486,6 +487,7 @@ struct IDEBus {
};
#define TYPE_IDE_DEVICE "ide-device"
typedef struct IDEDeviceClass IDEDeviceClass;
#define IDE_DEVICE(obj) \
OBJECT_CHECK(IDEDevice, (obj), TYPE_IDE_DEVICE)
#define IDE_DEVICE_CLASS(klass) \
@ -493,10 +495,10 @@ struct IDEBus {
#define IDE_DEVICE_GET_CLASS(obj) \
OBJECT_GET_CLASS(IDEDeviceClass, (obj), TYPE_IDE_DEVICE)
typedef struct IDEDeviceClass {
struct IDEDeviceClass {
DeviceClass parent_class;
void (*realize)(IDEDevice *dev, Error **errp);
} IDEDeviceClass;
};
struct IDEDevice {
DeviceState qdev;

6
include/hw/ide/pci.h
View file

@ -3,6 +3,7 @@
#include "hw/ide/internal.h"
#include "hw/pci/pci.h"
#include "qom/object.h"
#define BM_STATUS_DMAING 0x01
#define BM_STATUS_ERROR 0x02
@ -39,9 +40,10 @@ typedef struct BMDMAState {
} BMDMAState;
#define TYPE_PCI_IDE "pci-ide"
typedef struct PCIIDEState PCIIDEState;
#define PCI_IDE(obj) OBJECT_CHECK(PCIIDEState, (obj), TYPE_PCI_IDE)
typedef struct PCIIDEState {
struct PCIIDEState {
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
@ -52,7 +54,7 @@ typedef struct PCIIDEState {
MemoryRegion bmdma_bar;
MemoryRegion cmd_bar[2];
MemoryRegion data_bar[2];
} PCIIDEState;
};
static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
{

6
include/hw/input/adb.h
View file

@ -27,6 +27,7 @@
#define ADB_H
#include "hw/qdev-core.h"
#include "qom/object.h"
#define MAX_ADB_DEVICES 16
@ -42,6 +43,7 @@ typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
typedef bool ADBDeviceHasData(ADBDevice *d);
#define TYPE_ADB_DEVICE "adb-device"
typedef struct ADBDeviceClass ADBDeviceClass;
#define ADB_DEVICE(obj) OBJECT_CHECK(ADBDevice, (obj), TYPE_ADB_DEVICE)
struct ADBDevice {
@ -58,14 +60,14 @@ struct ADBDevice {
#define ADB_DEVICE_GET_CLASS(obj) \
OBJECT_GET_CLASS(ADBDeviceClass, (obj), TYPE_ADB_DEVICE)
typedef struct ADBDeviceClass {
struct ADBDeviceClass {
/*< private >*/
DeviceClass parent_class;
/*< public >*/
ADBDeviceRequest *devreq;
ADBDeviceHasData *devhasdata;
} ADBDeviceClass;
};
#define TYPE_ADB_BUS "apple-desktop-bus"
#define ADB_BUS(obj) OBJECT_CHECK(ADBBusState, (obj), TYPE_ADB_BUS)

3
include/hw/input/i8042.h
View file

@ -9,13 +9,14 @@
#define HW_INPUT_I8042_H
#include "hw/isa/isa.h"
#include "qom/object.h"
#define TYPE_I8042 "i8042"
typedef struct ISAKBDState ISAKBDState;
#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)
#define I8042_A20_LINE "a20"
typedef struct ISAKBDState ISAKBDState;
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
MemoryRegion *region, ram_addr_t size,

6
include/hw/intc/allwinner-a10-pic.h
View file

@ -2,8 +2,10 @@
#define ALLWINNER_A10_PIC_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_AW_A10_PIC "allwinner-a10-pic"
typedef struct AwA10PICState AwA10PICState;
#define AW_A10_PIC(obj) OBJECT_CHECK(AwA10PICState, (obj), TYPE_AW_A10_PIC)
#define AW_A10_PIC_VECTOR 0
@ -19,7 +21,7 @@
#define AW_A10_PIC_INT_NR 95
#define AW_A10_PIC_REG_NUM DIV_ROUND_UP(AW_A10_PIC_INT_NR, 32)
typedef struct AwA10PICState {
struct AwA10PICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -37,6 +39,6 @@ typedef struct AwA10PICState {
uint32_t enable[AW_A10_PIC_REG_NUM];
uint32_t mask[AW_A10_PIC_REG_NUM];
/*priority setting here*/
} AwA10PICState;
};
#endif

6
include/hw/intc/arm_gic.h
View file

@ -65,6 +65,7 @@
#define HW_ARM_GIC_H
#include "arm_gic_common.h"
#include "qom/object.h"
/* Number of SGI target-list bits */
#define GIC_TARGETLIST_BITS 8
@ -72,6 +73,7 @@
#define GIC_MIN_PRIORITY_BITS 4
#define TYPE_ARM_GIC "arm_gic"
typedef struct ARMGICClass ARMGICClass;
#define ARM_GIC(obj) \
OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC)
#define ARM_GIC_CLASS(klass) \
@ -79,12 +81,12 @@
#define ARM_GIC_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC)
typedef struct ARMGICClass {
struct ARMGICClass {
/*< private >*/
ARMGICCommonClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
} ARMGICClass;
};
#endif

11
include/hw/intc/arm_gic_common.h
View file

@ -22,6 +22,7 @@
#define HW_ARM_GIC_COMMON_H
#include "hw/sysbus.h"
#include "qom/object.h"
/* Maximum number of possible interrupts, determined by the GIC architecture */
#define GIC_MAXIRQ 1020
@ -61,7 +62,7 @@ typedef struct gic_irq_state {
uint8_t group;
} gic_irq_state;
typedef struct GICState {
struct GICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -143,9 +144,11 @@ typedef struct GICState {
bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? */
int dev_fd; /* kvm device fd if backed by kvm vgic support */
Error *migration_blocker;
} GICState;
};
typedef struct GICState GICState;
#define TYPE_ARM_GIC_COMMON "arm_gic_common"
typedef struct ARMGICCommonClass ARMGICCommonClass;
#define ARM_GIC_COMMON(obj) \
OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
#define ARM_GIC_COMMON_CLASS(klass) \
@ -153,14 +156,14 @@ typedef struct GICState {
#define ARM_GIC_COMMON_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
typedef struct ARMGICCommonClass {
struct ARMGICCommonClass {
/*< private >*/
SysBusDeviceClass parent_class;
/*< public >*/
void (*pre_save)(GICState *s);
void (*post_load)(GICState *s);
} ARMGICCommonClass;
};
void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
const MemoryRegionOps *ops,

6
include/hw/intc/arm_gicv3.h
View file

@ -13,20 +13,22 @@
#define HW_ARM_GICV3_H
#include "arm_gicv3_common.h"
#include "qom/object.h"
#define TYPE_ARM_GICV3 "arm-gicv3"
typedef struct ARMGICv3Class ARMGICv3Class;
#define ARM_GICV3(obj) OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3)
#define ARM_GICV3_CLASS(klass) \
OBJECT_CLASS_CHECK(ARMGICv3Class, (klass), TYPE_ARM_GICV3)
#define ARM_GICV3_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMGICv3Class, (obj), TYPE_ARM_GICV3)
typedef struct ARMGICv3Class {
struct ARMGICv3Class {
/*< private >*/
ARMGICv3CommonClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
} ARMGICv3Class;
};
#endif

6
include/hw/intc/arm_gicv3_common.h
View file

@ -26,6 +26,7 @@
#include "hw/sysbus.h"
#include "hw/intc/arm_gic_common.h"
#include "qom/object.h"
/*
* Maximum number of possible interrupts, determined by the GIC architecture.
@ -279,6 +280,7 @@ GICV3_BITMAP_ACCESSORS(level)
GICV3_BITMAP_ACCESSORS(edge_trigger)
#define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
typedef struct ARMGICv3CommonClass ARMGICv3CommonClass;
#define ARM_GICV3_COMMON(obj) \
OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3_COMMON)
#define ARM_GICV3_COMMON_CLASS(klass) \
@ -286,14 +288,14 @@ GICV3_BITMAP_ACCESSORS(edge_trigger)
#define ARM_GICV3_COMMON_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMGICv3CommonClass, (obj), TYPE_ARM_GICV3_COMMON)
typedef struct ARMGICv3CommonClass {
struct ARMGICv3CommonClass {
/*< private >*/
SysBusDeviceClass parent_class;
/*< public >*/
void (*pre_save)(GICv3State *s);
void (*post_load)(GICv3State *s);
} ARMGICv3CommonClass;
};
void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
const MemoryRegionOps *ops, Error **errp);

3
include/hw/intc/arm_gicv3_its_common.h
View file

@ -23,6 +23,7 @@
#include "hw/sysbus.h"
#include "hw/intc/arm_gicv3_common.h"
#include "qom/object.h"
#define ITS_CONTROL_SIZE 0x10000
#define ITS_TRANS_SIZE 0x10000
@ -64,6 +65,7 @@ typedef struct GICv3ITSState GICv3ITSState;
void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops);
#define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
#define ARM_GICV3_ITS_COMMON(obj) \
OBJECT_CHECK(GICv3ITSState, (obj), TYPE_ARM_GICV3_ITS_COMMON)
#define ARM_GICV3_ITS_COMMON_CLASS(klass) \
@ -81,6 +83,5 @@ struct GICv3ITSCommonClass {
void (*post_load)(GICv3ITSState *s);
};
typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
#endif

6
include/hw/intc/armv7m_nvic.h
View file

@ -13,9 +13,11 @@
#include "target/arm/cpu.h"
#include "hw/sysbus.h"
#include "hw/timer/armv7m_systick.h"
#include "qom/object.h"
#define TYPE_NVIC "armv7m_nvic"
typedef struct NVICState NVICState;
#define NVIC(obj) \
OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
@ -35,7 +37,7 @@ typedef struct VecInfo {
uint8_t level; /* exceptions <=15 never set level */
} VecInfo;
typedef struct NVICState {
struct NVICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -88,6 +90,6 @@ typedef struct NVICState {
qemu_irq sysresetreq;
SysTickState systick[M_REG_NUM_BANKS];
} NVICState;
};
#endif

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