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target/riscv: Consolidate RV32/64 32-bit instructions

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This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.

This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-04-24 13:34:12 +10:00
parent 4bb85634af
commit daf866b606
14 changed files with 166 additions and 150 deletions
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2
target/riscv/meson.build
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@ -7,7 +7,7 @@ gen32 = [
gen64 = [
decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
]
riscv_ss = ss.source_set()