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Misc HW patch queue
- Remove unused MIPS SAAR* registers (Phil) - Remove warning when testing the TC58128 NAND EEPROM (Peter) - KConfig cleanups around ISA SuperI/O and MIPS (Paolo) - QDev API uses sanitization (Philippe) - Split AHCI model as PCI / SysBus (Philippe) - Add SMP support to SPARC Leon3 board (Clément) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmXOUD4ACgkQ4+MsLN6t wN6gWRAAjf+6Z9VUvvHqZoaSJW49k+GRUelTI2tyN+eGfetAx9dk8aIbpbV1X12d pc56jsSi6ICT7baCegtxHszhYJr2e9A2QLCAOJt+Oz87kEGes3ONVVKAk7pwjKxt m8pmU3uXWgFvU6PoFBhGBa6LiZBulgLNXBUwzmEhc9PpPkR49ULdDp/qxtWvxOV5 xYBktFlkiT+AvHq3QWCnDIaw+pH5ghEq9BI4xFOvvvqSqdHEqsGAaiKPa9Po0Gfz Ap9qsm4FxKxhGoeQWtAIP8TvN3pFFSXMysziP6Xt1rffKsvF9ioghGKRM6BgQfqD ZetjcFbcf7dQu3zZVy8ljYcymMxfZcWWVVq4CMC68lPQE97hz1CT3PJjgd77dKfi z60uRkOGaiPW5iIGT9+vdQxZ5K3HivKyjuHOdV8V4HnWO3oqgfDtNHn5RKed0qUg g1FoWriJGsDixdx1vd0EoH2/oTxy4HIsFv7a1OjiZyBLjO+EeEZ3+H9pqUHqBxva +Dv70z9F1sv5dzcUXH+oCgTbnKlJ90Q+e3vj0wGdlBncVsgIwbtgqYelhUEl+xJX Mu6KNUo5ANVP38ZKG0GSMCZHfcUjc5s+5rG55NbTN0HiF56a6D2KlQAuXdUsGE1J 7i4cwipJmfxzbdPDlSb3kBxm5pFexEk6nROF9kTHQj3ZBMMvIls= =nOX+ -----END PGP SIGNATURE----- Merge tag 'hw-misc-20240215' of https://github.com/philmd/qemu into staging Misc HW patch queue - Remove unused MIPS SAAR* registers (Phil) - Remove warning when testing the TC58128 NAND EEPROM (Peter) - KConfig cleanups around ISA SuperI/O and MIPS (Paolo) - QDev API uses sanitization (Philippe) - Split AHCI model as PCI / SysBus (Philippe) - Add SMP support to SPARC Leon3 board (Clément) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmXOUD4ACgkQ4+MsLN6t # wN6gWRAAjf+6Z9VUvvHqZoaSJW49k+GRUelTI2tyN+eGfetAx9dk8aIbpbV1X12d # pc56jsSi6ICT7baCegtxHszhYJr2e9A2QLCAOJt+Oz87kEGes3ONVVKAk7pwjKxt # m8pmU3uXWgFvU6PoFBhGBa6LiZBulgLNXBUwzmEhc9PpPkR49ULdDp/qxtWvxOV5 # xYBktFlkiT+AvHq3QWCnDIaw+pH5ghEq9BI4xFOvvvqSqdHEqsGAaiKPa9Po0Gfz # Ap9qsm4FxKxhGoeQWtAIP8TvN3pFFSXMysziP6Xt1rffKsvF9ioghGKRM6BgQfqD # ZetjcFbcf7dQu3zZVy8ljYcymMxfZcWWVVq4CMC68lPQE97hz1CT3PJjgd77dKfi # z60uRkOGaiPW5iIGT9+vdQxZ5K3HivKyjuHOdV8V4HnWO3oqgfDtNHn5RKed0qUg # g1FoWriJGsDixdx1vd0EoH2/oTxy4HIsFv7a1OjiZyBLjO+EeEZ3+H9pqUHqBxva # +Dv70z9F1sv5dzcUXH+oCgTbnKlJ90Q+e3vj0wGdlBncVsgIwbtgqYelhUEl+xJX # Mu6KNUo5ANVP38ZKG0GSMCZHfcUjc5s+5rG55NbTN0HiF56a6D2KlQAuXdUsGE1J # 7i4cwipJmfxzbdPDlSb3kBxm5pFexEk6nROF9kTHQj3ZBMMvIls= # =nOX+ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 15 Feb 2024 17:56:14 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20240215' of https://github.com/philmd/qemu: (56 commits) hw/ide/ich9: Use AHCIPCIState typedef hw/ide/ahci: Move SysBus definitions to 'ahci-sysbus.h' hw/ide/ahci: Remove SysbusAHCIState::num_ports field hw/ide/ahci: Do not pass 'ports' argument to ahci_realize() hw/ide/ahci: Convert AHCIState::ports to unsigned hw/ide/ahci: Pass AHCI context to ahci_ide_create_devs() hw/ide/ahci: Inline ahci_get_num_ports() hw/ide/ahci: Rename AHCI PCI function as 'pdev' hw/ide/ahci: Expose AHCIPCIState structure hw/i386/q35: Use DEVICE() cast macro with PCIDevice object hw/i386/q35: Simplify pc_q35_init() since PCI is always enabled MAINTAINERS: Add myself as reviewer for TCG Plugins MAINTAINERS: replace Fabien by myself as Leon3 maintainer hw/sparc/leon3: Initialize GPIO before realizing CPU devices hw/sparc/leon3: Pass DeviceState opaque argument to leon3_start_cpu() hw/sparc/leon3: Pass DeviceState opaque argument to leon3_set_pil_in() hw/sparc/leon3: check cpu_id in the tiny bootloader hw/sparc/leon3: implement multiprocessor hw/sparc/leon3: remove SP initialization target/sparc: implement asr17 feature for smp ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
da96ad4a6a
59 changed files with 488 additions and 460 deletions
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@ -123,14 +123,17 @@ static bool macio_realize_ide(MacIOState *s, MACIOIDEState *ide,
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(ide);
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sysbus_connect_irq(sbd, 0, irq0);
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sysbus_connect_irq(sbd, 1, irq1);
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qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid);
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object_property_set_link(OBJECT(ide), "dbdma", OBJECT(&s->dbdma),
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&error_abort);
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macio_ide_register_dma(ide);
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if (!qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp)) {
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return false;
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}
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sysbus_connect_irq(sbd, 0, irq0);
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sysbus_connect_irq(sbd, 1, irq1);
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return qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp);
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return true;
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}
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static void macio_oldworld_realize(PCIDevice *d, Error **errp)
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@ -86,7 +86,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
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return tag->ITCAddressMap[index];
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}
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void itc_reconfigure(MIPSITUState *tag)
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static void itc_reconfigure(MIPSITUState *tag)
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{
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uint64_t *am = &tag->ITCAddressMap[0];
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MemoryRegion *mr = &tag->storage_io;
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@ -94,12 +94,6 @@ void itc_reconfigure(MIPSITUState *tag)
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uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
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bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
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if (tag->saar) {
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address = (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4;
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size = 1ULL << ((tag->saar[0] >> 1) & 0x1f);
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is_enabled = tag->saar[0] & 1;
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}
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memory_region_transaction_begin();
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if (!(size & (size - 1))) {
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memory_region_set_size(mr, size);
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@ -158,12 +152,7 @@ static inline ITCView get_itc_view(hwaddr addr)
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static inline int get_cell_stride_shift(const MIPSITUState *s)
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{
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/* Minimum interval (for EntryGain = 0) is 128 B */
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if (s->saar) {
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return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) &
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ITC_ICR0_BLK_GRAIN_MASK);
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} else {
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return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
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}
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return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
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}
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static inline ITCStorageCell *get_cell(MIPSITUState *s,
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@ -516,7 +505,6 @@ static void mips_itu_init(Object *obj)
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static void mips_itu_realize(DeviceState *dev, Error **errp)
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{
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MIPSITUState *s = MIPS_ITU(dev);
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CPUMIPSState *env;
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if (s->num_fifo > ITC_FIFO_NUM_MAX) {
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error_setg(errp, "Exceed maximum number of FIFO cells: %d",
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@ -528,15 +516,6 @@ static void mips_itu_realize(DeviceState *dev, Error **errp)
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s->num_semaphores);
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return;
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}
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if (!s->cpu0) {
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error_setg(errp, "Missing 'cpu[0]' property");
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return;
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}
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env = &MIPS_CPU(s->cpu0)->env;
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if (env->saarp) {
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s->saar = env->CP0_SAAR;
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}
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s->cell = g_new(ITCStorageCell, get_num_cells(s));
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}
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@ -545,15 +524,10 @@ static void mips_itu_reset(DeviceState *dev)
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{
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MIPSITUState *s = MIPS_ITU(dev);
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if (s->saar) {
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s->saar[0] = 0x11 << 1;
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s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM;
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} else {
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s->ITCAddressMap[0] = 0;
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s->ITCAddressMap[1] =
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s->ITCAddressMap[0] = 0;
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s->ITCAddressMap[1] =
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((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
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(get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
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}
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itc_reconfigure(s);
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itc_reset_cells(s);
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@ -564,7 +538,6 @@ static Property mips_itu_properties[] = {
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ITC_FIFO_NUM_MAX),
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DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores,
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ITC_SEMAPH_NUM_MAX),
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DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, ArchCPU *),
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DEFINE_PROP_END_OF_LIST(),
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};
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