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target/sparc: Merge LDFSR, LDXFSR implementations

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Combine the helper to a single set_fsr().
Perform the mask and merge inline.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-05 02:31:25 -07:00
parent 3d3c06737b
commit da68140604
3 changed files with 16 additions and 46 deletions
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42
target/sparc/translate.c
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@ -45,7 +45,6 @@
# define gen_helper_clear_softint(E, S) qemu_build_not_reached()
# define gen_helper_done(E) qemu_build_not_reached()
# define gen_helper_flushw(E) qemu_build_not_reached()
# define gen_helper_ldxfsr(D, E, A, B) qemu_build_not_reached()
# define gen_helper_rdccr(D, E) qemu_build_not_reached()
# define gen_helper_rdcwp(D, E) qemu_build_not_reached()
# define gen_helper_restored(E) qemu_build_not_reached()
@ -63,6 +62,8 @@
# define gen_helper_write_softint(E, S) qemu_build_not_reached()
# define gen_helper_wrpil(E, S) qemu_build_not_reached()
# define gen_helper_wrpstate(E, S) qemu_build_not_reached()
# define FSR_LDXFSR_MASK 0
# define FSR_LDXFSR_OLDMASK 0
# define MAXTL_MASK 0
#endif
@ -4675,44 +4676,27 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a)
return true;
}
static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a)
static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop,
target_ulong new_mask, target_ulong old_mask)
{
TCGv addr;
TCGv_i32 tmp;
addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
TCGv tmp, addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
if (addr == NULL) {
return false;
}
if (gen_trap_ifnofpu(dc)) {
return true;
}
tmp = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_TEUL | MO_ALIGN);
gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, tmp);
tmp = tcg_temp_new();
tcg_gen_qemu_ld_tl(tmp, addr, dc->mem_idx, mop | MO_ALIGN);
tcg_gen_andi_tl(tmp, tmp, new_mask);
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, old_mask);
tcg_gen_or_tl(cpu_fsr, cpu_fsr, tmp);
gen_helper_set_fsr(tcg_env, cpu_fsr);
return advance_pc(dc);
}
static bool trans_LDXFSR(DisasContext *dc, arg_r_r_ri *a)
{
TCGv addr;
TCGv_i64 tmp;
if (!avail_64(dc)) {
return false;
}
addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
if (addr == NULL) {
return false;
}
if (gen_trap_ifnofpu(dc)) {
return true;
}
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tmp, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN);
gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, tmp);
return advance_pc(dc);
}
TRANS(LDFSR, ALL, do_ldfsr, a, MO_TEUL, FSR_LDFSR_MASK, FSR_LDFSR_OLDMASK)
TRANS(LDXFSR, 64, do_ldfsr, a, MO_TEUQ, FSR_LDXFSR_MASK, FSR_LDXFSR_OLDMASK)
static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop)
{