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include: update Linux headers to 4.21-rc1/5.0-rc1
This is simply running the newly-updated script on Linux, in order to obtain the new header files and all the other updates from the recent Linux merge window. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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25 changed files with 2243 additions and 1589 deletions
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@ -303,6 +303,71 @@ struct vfio_region_info_cap_type {
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#define VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG (2)
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#define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3)
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#define VFIO_REGION_TYPE_GFX (1)
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#define VFIO_REGION_SUBTYPE_GFX_EDID (1)
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/**
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* struct vfio_region_gfx_edid - EDID region layout.
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*
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* Set display link state and EDID blob.
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*
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* The EDID blob has monitor information such as brand, name, serial
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* number, physical size, supported video modes and more.
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*
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* This special region allows userspace (typically qemu) set a virtual
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* EDID for the virtual monitor, which allows a flexible display
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* configuration.
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*
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* For the edid blob spec look here:
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* https://en.wikipedia.org/wiki/Extended_Display_Identification_Data
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*
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* On linux systems you can find the EDID blob in sysfs:
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* /sys/class/drm/${card}/${connector}/edid
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*
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* You can use the edid-decode ulility (comes with xorg-x11-utils) to
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* decode the EDID blob.
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*
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* @edid_offset: location of the edid blob, relative to the
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* start of the region (readonly).
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* @edid_max_size: max size of the edid blob (readonly).
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* @edid_size: actual edid size (read/write).
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* @link_state: display link state (read/write).
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* VFIO_DEVICE_GFX_LINK_STATE_UP: Monitor is turned on.
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* VFIO_DEVICE_GFX_LINK_STATE_DOWN: Monitor is turned off.
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* @max_xres: max display width (0 == no limitation, readonly).
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* @max_yres: max display height (0 == no limitation, readonly).
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*
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* EDID update protocol:
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* (1) set link-state to down.
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* (2) update edid blob and size.
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* (3) set link-state to up.
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*/
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struct vfio_region_gfx_edid {
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__u32 edid_offset;
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__u32 edid_max_size;
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__u32 edid_size;
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__u32 max_xres;
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__u32 max_yres;
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__u32 link_state;
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#define VFIO_DEVICE_GFX_LINK_STATE_UP 1
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#define VFIO_DEVICE_GFX_LINK_STATE_DOWN 2
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};
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/*
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* 10de vendor sub-type
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*
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* NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space.
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*/
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#define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1)
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/*
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* 1014 vendor sub-type
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*
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* IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU
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* to do TLB invalidation on a GPU.
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*/
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#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1)
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/*
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* The MSIX mappable capability informs that MSIX data of a BAR can be mmapped
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* which allows direct access to non-MSIX registers which happened to be within
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@ -313,6 +378,33 @@ struct vfio_region_info_cap_type {
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*/
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#define VFIO_REGION_INFO_CAP_MSIX_MAPPABLE 3
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/*
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* Capability with compressed real address (aka SSA - small system address)
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* where GPU RAM is mapped on a system bus. Used by a GPU for DMA routing
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* and by the userspace to associate a NVLink bridge with a GPU.
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*/
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#define VFIO_REGION_INFO_CAP_NVLINK2_SSATGT 4
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struct vfio_region_info_cap_nvlink2_ssatgt {
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struct vfio_info_cap_header header;
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__u64 tgt;
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};
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/*
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* Capability with an NVLink link speed. The value is read by
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* the NVlink2 bridge driver from the bridge's "ibm,nvlink-speed"
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* property in the device tree. The value is fixed in the hardware
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* and failing to provide the correct value results in the link
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* not working with no indication from the driver why.
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*/
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#define VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD 5
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struct vfio_region_info_cap_nvlink2_lnkspd {
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struct vfio_info_cap_header header;
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__u32 link_speed;
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__u32 __pad;
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};
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/**
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* VFIO_DEVICE_GET_IRQ_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 9,
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* struct vfio_irq_info)
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