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hw/misc: Add support for NPCM8XX GCR

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-8-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Hao Wu 2025-02-19 10:45:58 -08:00 • committed by Peter Maydell
parent 8ca2021b9d
commit d9ffb75f2a
2 changed files with 134 additions and 5 deletions
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133
hw/misc/npcm_gcr.c
View file

@ -1,5 +1,5 @@
/*
* Nuvoton NPCM7xx System Global Control Registers.
* Nuvoton NPCM7xx/8xx System Global Control Registers.
*
* Copyright 2020 Google LLC
*
@ -83,6 +83,118 @@ static const uint32_t npcm7xx_cold_reset_values[NPCM7XX_GCR_NR_REGS] = {
[NPCM7XX_GCR_USB2PHYCTL] = 0x034730e4,
};
enum NPCM8xxGCRRegisters {
NPCM8XX_GCR_PDID,
NPCM8XX_GCR_PWRON,
NPCM8XX_GCR_MISCPE = 0x014 / sizeof(uint32_t),
NPCM8XX_GCR_FLOCKR2 = 0x020 / sizeof(uint32_t),
NPCM8XX_GCR_FLOCKR3,
NPCM8XX_GCR_A35_MODE = 0x034 / sizeof(uint32_t),
NPCM8XX_GCR_SPSWC,
NPCM8XX_GCR_INTCR,
NPCM8XX_GCR_INTSR,
NPCM8XX_GCR_HIFCR = 0x050 / sizeof(uint32_t),
NPCM8XX_GCR_INTCR2 = 0x060 / sizeof(uint32_t),
NPCM8XX_GCR_SRCNT = 0x068 / sizeof(uint32_t),
NPCM8XX_GCR_RESSR,
NPCM8XX_GCR_RLOCKR1,
NPCM8XX_GCR_FLOCKR1,
NPCM8XX_GCR_DSCNT,
NPCM8XX_GCR_MDLR,
NPCM8XX_GCR_SCRPAD_C = 0x080 / sizeof(uint32_t),
NPCM8XX_GCR_SCRPAD_B,
NPCM8XX_GCR_DAVCLVLR = 0x098 / sizeof(uint32_t),
NPCM8XX_GCR_INTCR3,
NPCM8XX_GCR_PCIRCTL = 0x0a0 / sizeof(uint32_t),
NPCM8XX_GCR_VSINTR,
NPCM8XX_GCR_SD2SUR1 = 0x0b4 / sizeof(uint32_t),
NPCM8XX_GCR_SD2SUR2,
NPCM8XX_GCR_INTCR4 = 0x0c0 / sizeof(uint32_t),
NPCM8XX_GCR_CPCTL = 0x0d0 / sizeof(uint32_t),
NPCM8XX_GCR_CP2BST,
NPCM8XX_GCR_B2CPNT,
NPCM8XX_GCR_CPPCTL,
NPCM8XX_GCR_I2CSEGSEL = 0x0e0 / sizeof(uint32_t),
NPCM8XX_GCR_I2CSEGCTL,
NPCM8XX_GCR_VSRCR,
NPCM8XX_GCR_MLOCKR,
NPCM8XX_GCR_SCRPAD = 0x13c / sizeof(uint32_t),
NPCM8XX_GCR_USB1PHYCTL,
NPCM8XX_GCR_USB2PHYCTL,
NPCM8XX_GCR_USB3PHYCTL,
NPCM8XX_GCR_MFSEL1 = 0x260 / sizeof(uint32_t),
NPCM8XX_GCR_MFSEL2,
NPCM8XX_GCR_MFSEL3,
NPCM8XX_GCR_MFSEL4,
NPCM8XX_GCR_MFSEL5,
NPCM8XX_GCR_MFSEL6,
NPCM8XX_GCR_MFSEL7,
NPCM8XX_GCR_MFSEL_LK1 = 0x280 / sizeof(uint32_t),
NPCM8XX_GCR_MFSEL_LK2,
NPCM8XX_GCR_MFSEL_LK3,
NPCM8XX_GCR_MFSEL_LK4,
NPCM8XX_GCR_MFSEL_LK5,
NPCM8XX_GCR_MFSEL_LK6,
NPCM8XX_GCR_MFSEL_LK7,
NPCM8XX_GCR_MFSEL_SET1 = 0x2a0 / sizeof(uint32_t),
NPCM8XX_GCR_MFSEL_SET2,
NPCM8XX_GCR_MFSEL_SET3,
NPCM8XX_GCR_MFSEL_SET4,
NPCM8XX_GCR_MFSEL_SET5,
NPCM8XX_GCR_MFSEL_SET6,
NPCM8XX_GCR_MFSEL_SET7,
NPCM8XX_GCR_MFSEL_CLR1 = 0x2c0 / sizeof(uint32_t),
NPCM8XX_GCR_MFSEL_CLR2,
NPCM8XX_GCR_MFSEL_CLR3,
NPCM8XX_GCR_MFSEL_CLR4,
NPCM8XX_GCR_MFSEL_CLR5,
NPCM8XX_GCR_MFSEL_CLR6,
NPCM8XX_GCR_MFSEL_CLR7,
NPCM8XX_GCR_WD0RCRLK = 0x400 / sizeof(uint32_t),
NPCM8XX_GCR_WD1RCRLK,
NPCM8XX_GCR_WD2RCRLK,
NPCM8XX_GCR_SWRSTC1LK,
NPCM8XX_GCR_SWRSTC2LK,
NPCM8XX_GCR_SWRSTC3LK,
NPCM8XX_GCR_TIPRSTCLK,
NPCM8XX_GCR_CORSTCLK,
NPCM8XX_GCR_WD0RCRBLK,
NPCM8XX_GCR_WD1RCRBLK,
NPCM8XX_GCR_WD2RCRBLK,
NPCM8XX_GCR_SWRSTC1BLK,
NPCM8XX_GCR_SWRSTC2BLK,
NPCM8XX_GCR_SWRSTC3BLK,
NPCM8XX_GCR_TIPRSTCBLK,
NPCM8XX_GCR_CORSTCBLK,
/* 64 scratch pad registers start here. 0xe00 ~ 0xefc */
NPCM8XX_GCR_SCRPAD_00 = 0xe00 / sizeof(uint32_t),
/* 32 semaphore registers start here. 0xf00 ~ 0xf7c */
NPCM8XX_GCR_GP_SEMFR_00 = 0xf00 / sizeof(uint32_t),
NPCM8XX_GCR_GP_SEMFR_31 = 0xf7c / sizeof(uint32_t),
};
static const uint32_t npcm8xx_cold_reset_values[NPCM8XX_GCR_NR_REGS] = {
[NPCM8XX_GCR_PDID] = 0x04a35850, /* Arbel A1 */
[NPCM8XX_GCR_MISCPE] = 0x0000ffff,
[NPCM8XX_GCR_A35_MODE] = 0xfff4ff30,
[NPCM8XX_GCR_SPSWC] = 0x00000003,
[NPCM8XX_GCR_INTCR] = 0x0010035e,
[NPCM8XX_GCR_HIFCR] = 0x0000004e,
[NPCM8XX_GCR_SD2SUR1] = 0xfdc80000,
[NPCM8XX_GCR_SD2SUR2] = 0x5200b130,
[NPCM8XX_GCR_INTCR2] = (1U << 19), /* DDR initialized */
[NPCM8XX_GCR_RESSR] = 0x80000000,
[NPCM8XX_GCR_DAVCLVLR] = 0x5a00f3cf,
[NPCM8XX_GCR_INTCR3] = 0x5e001002,
[NPCM8XX_GCR_VSRCR] = 0x00004800,
[NPCM8XX_GCR_SCRPAD] = 0x00000008,
[NPCM8XX_GCR_USB1PHYCTL] = 0x034730e4,
[NPCM8XX_GCR_USB2PHYCTL] = 0x034730e4,
[NPCM8XX_GCR_USB3PHYCTL] = 0x034730e4,
/* All 32 semaphores should be initialized to 1. */
[NPCM8XX_GCR_GP_SEMFR_00...NPCM8XX_GCR_GP_SEMFR_31] = 0x00000001,
};
static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t reg = offset / sizeof(uint32_t);
@ -224,8 +336,8 @@ static void npcm_gcr_init(Object *obj)
static const VMStateDescription vmstate_npcm_gcr = {
.name = "npcm-gcr",
.version_id = 1,
.minimum_version_id = 1,
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, NPCMGCRState, NPCM_GCR_MAX_NR_REGS),
VMSTATE_END_OF_LIST(),
@ -260,6 +372,16 @@ static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
c->cold_reset_values = npcm7xx_cold_reset_values;
}
static void npcm8xx_gcr_class_init(ObjectClass *klass, void *data)
{
NPCMGCRClass *c = NPCM_GCR_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "NPCM8xx System Global Control Registers";
c->nr_regs = NPCM8XX_GCR_NR_REGS;
c->cold_reset_values = npcm8xx_cold_reset_values;
}
static const TypeInfo npcm_gcr_info[] = {
{
.name = TYPE_NPCM_GCR,
@ -275,5 +397,10 @@ static const TypeInfo npcm_gcr_info[] = {
.parent = TYPE_NPCM_GCR,
.class_init = npcm7xx_gcr_class_init,
},
{
.name = TYPE_NPCM8XX_GCR,
.parent = TYPE_NPCM_GCR,
.class_init = npcm8xx_gcr_class_init,
},
};
DEFINE_TYPES(npcm_gcr_info)

6
include/hw/misc/npcm_gcr.h
View file

@ -1,5 +1,5 @@
/*
* Nuvoton NPCM7xx System Global Control Registers.
* Nuvoton NPCM7xx/8xx System Global Control Registers.
*
* Copyright 2020 Google LLC
*
@ -54,8 +54,9 @@
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.
*/
#define NPCM_GCR_MAX_NR_REGS NPCM7XX_GCR_NR_REGS
#define NPCM_GCR_MAX_NR_REGS NPCM8XX_GCR_NR_REGS
#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
#define NPCM8XX_GCR_NR_REGS (0xf80 / sizeof(uint32_t))
typedef struct NPCMGCRState {
SysBusDevice parent;
@ -78,6 +79,7 @@ typedef struct NPCMGCRClass {
#define TYPE_NPCM_GCR "npcm-gcr"
#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
#define TYPE_NPCM8XX_GCR "npcm8xx-gcr"
OBJECT_DECLARE_TYPE(NPCMGCRState, NPCMGCRClass, NPCM_GCR)
#endif /* NPCM_GCR_H */