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target/ppc: Add helpers for fadds, fsubs, fdivs

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Use float64r32_{add,sub,div}.  Fixes a double-rounding issue with
performing the compuation in float64 and then rounding afterward.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-31-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Richard Henderson 2021-12-17 17:57:16 +01:00 • committed by Cédric Le Goater
parent 41ae890d08
commit d9e792a1c1
3 changed files with 47 additions and 7 deletions
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40
target/ppc/fpu_helper.c
View file

@ -521,6 +521,18 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
return ret; return ret;
} }
/* fadds - fadds. */
float64 helper_fadds(CPUPPCState *env, float64 arg1, float64 arg2)
{
float64 ret = float64r32_add(arg1, arg2, &env->fp_status);
int flags = get_float_exception_flags(&env->fp_status);
if (unlikely(flags & float_flag_invalid)) {
float_invalid_op_addsub(env, flags, 1, GETPC());
}
return ret;
}
/* fsub - fsub. */ /* fsub - fsub. */
float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
{ {
@ -534,6 +546,18 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
return ret; return ret;
} }
/* fsubs - fsubs. */
float64 helper_fsubs(CPUPPCState *env, float64 arg1, float64 arg2)
{
float64 ret = float64r32_sub(arg1, arg2, &env->fp_status);
int flags = get_float_exception_flags(&env->fp_status);
if (unlikely(flags & float_flag_invalid)) {
float_invalid_op_addsub(env, flags, 1, GETPC());
}
return ret;
}
static void float_invalid_op_mul(CPUPPCState *env, int flags, static void float_invalid_op_mul(CPUPPCState *env, int flags,
bool set_fprc, uintptr_t retaddr) bool set_fprc, uintptr_t retaddr)
{ {
@ -585,6 +609,22 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
return ret; return ret;
} }
/* fdivs - fdivs. */
float64 helper_fdivs(CPUPPCState *env, float64 arg1, float64 arg2)
{
float64 ret = float64r32_div(arg1, arg2, &env->fp_status);
int flags = get_float_exception_flags(&env->fp_status);
if (unlikely(flags & float_flag_invalid)) {
float_invalid_op_div(env, flags, 1, GETPC());
}
if (unlikely(flags & float_flag_divbyzero)) {
float_zero_divide_excp(env, GETPC());
}
return ret;
}
static uint64_t float_invalid_cvt(CPUPPCState *env, int flags, static uint64_t float_invalid_cvt(CPUPPCState *env, int flags,
uint64_t ret, uint64_t ret_nan, uint64_t ret, uint64_t ret_nan,
bool set_fprc, uintptr_t retaddr) bool set_fprc, uintptr_t retaddr)

3
target/ppc/helper.h
View file

@ -94,9 +94,12 @@ DEF_HELPER_2(frip, i64, env, i64)
DEF_HELPER_2(frim, i64, env, i64) DEF_HELPER_2(frim, i64, env, i64)
DEF_HELPER_3(fadd, f64, env, f64, f64) DEF_HELPER_3(fadd, f64, env, f64, f64)
DEF_HELPER_3(fadds, f64, env, f64, f64)
DEF_HELPER_3(fsub, f64, env, f64, f64) DEF_HELPER_3(fsub, f64, env, f64, f64)
DEF_HELPER_3(fsubs, f64, env, f64, f64)
DEF_HELPER_3(fmul, f64, env, f64, f64) DEF_HELPER_3(fmul, f64, env, f64, f64)
DEF_HELPER_3(fdiv, f64, env, f64, f64) DEF_HELPER_3(fdiv, f64, env, f64, f64)
DEF_HELPER_3(fdivs, f64, env, f64, f64)
DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fmadd, i64, env, i64, i64, i64)
DEF_HELPER_4(fmsub, i64, env, i64, i64, i64) DEF_HELPER_4(fmsub, i64, env, i64, i64, i64)
DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64)

11
target/ppc/translate/fp-impl.c.inc
View file

@ -68,7 +68,7 @@ static void gen_f##name(DisasContext *ctx) \
_GEN_FLOAT_ACB(name, 0x3F, op2, set_fprf, type); \ _GEN_FLOAT_ACB(name, 0x3F, op2, set_fprf, type); \
_GEN_FLOAT_ACB(name##s, 0x3B, op2, set_fprf, type); _GEN_FLOAT_ACB(name##s, 0x3B, op2, set_fprf, type);
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ #define _GEN_FLOAT_AB(name, op1, op2, inval, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \ static void gen_f##name(DisasContext *ctx) \
{ \ { \
TCGv_i64 t0; \ TCGv_i64 t0; \
@ -84,10 +84,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \ gen_reset_fpstatus(); \
get_fpr(t0, rA(ctx->opcode)); \ get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rB(ctx->opcode)); \ get_fpr(t1, rB(ctx->opcode)); \
gen_helper_f##op(t2, cpu_env, t0, t1); \ gen_helper_f##name(t2, cpu_env, t0, t1); \
if (isfloat) { \
gen_helper_frsp(t2, cpu_env, t2); \
} \
set_fpr(rD(ctx->opcode), t2); \ set_fpr(rD(ctx->opcode), t2); \
if (set_fprf) { \ if (set_fprf) { \
gen_compute_fprf_float64(t2); \ gen_compute_fprf_float64(t2); \
@ -100,8 +97,8 @@ static void gen_f##name(DisasContext *ctx) \
tcg_temp_free_i64(t2); \ tcg_temp_free_i64(t2); \
} }
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ _GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); \
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); _GEN_FLOAT_AB(name##s, 0x3B, op2, inval, set_fprf, type);
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \ static void gen_f##name(DisasContext *ctx) \