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linux headers: update against Linux 5.2-rc1
commit a188339ca5a396acc588e5851ed7e19f66b0ebd9 Signed-off-by: Cornelia Huck <cohuck@redhat.com>
This commit is contained in:
Cornelia Huck
parent
b1b9e0dc78
commit
d9cb433615
36 changed files with 906 additions and 143 deletions
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@ -252,9 +252,17 @@ struct ethtool_tunable {
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#define DOWNSHIFT_DEV_DEFAULT_COUNT 0xff
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#define DOWNSHIFT_DEV_DISABLE 0
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/* Time in msecs after which link is reported as down
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* 0 = lowest time supported by the PHY
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* 0xff = off, link down detection according to standard
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*/
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#define ETHTOOL_PHY_FAST_LINK_DOWN_ON 0
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#define ETHTOOL_PHY_FAST_LINK_DOWN_OFF 0xff
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enum phy_tunable_id {
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ETHTOOL_PHY_ID_UNSPEC,
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ETHTOOL_PHY_DOWNSHIFT,
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ETHTOOL_PHY_FAST_LINK_DOWN,
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/*
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* Add your fresh new phy tunable attribute above and remember to update
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* phy_tunable_strings[] in net/core/ethtool.c
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@ -1432,6 +1440,13 @@ enum ethtool_link_mode_bit_indices {
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ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29,
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ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30,
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ETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31,
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/* Last allowed bit for __ETHTOOL_LINK_MODE_LEGACY_MASK is bit
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* 31. Please do NOT define any SUPPORTED_* or ADVERTISED_*
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* macro for bits > 31. The only way to use indices > 31 is to
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* use the new ETHTOOL_GLINKSETTINGS/ETHTOOL_SLINKSETTINGS API.
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*/
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ETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32,
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ETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33,
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ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34,
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@ -1453,15 +1468,24 @@ enum ethtool_link_mode_bit_indices {
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ETHTOOL_LINK_MODE_FEC_NONE_BIT = 49,
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ETHTOOL_LINK_MODE_FEC_RS_BIT = 50,
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ETHTOOL_LINK_MODE_FEC_BASER_BIT = 51,
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ETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52,
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ETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53,
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ETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54,
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ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55,
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ETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56,
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ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57,
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ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58,
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ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59,
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ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60,
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ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61,
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ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62,
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ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63,
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ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,
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ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65,
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ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,
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/* Last allowed bit for __ETHTOOL_LINK_MODE_LEGACY_MASK is bit
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* 31. Please do NOT define any SUPPORTED_* or ADVERTISED_*
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* macro for bits > 31. The only way to use indices > 31 is to
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* use the new ETHTOOL_GLINKSETTINGS/ETHTOOL_SLINKSETTINGS API.
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*/
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__ETHTOOL_LINK_MODE_LAST
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= ETHTOOL_LINK_MODE_FEC_BASER_BIT,
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/* must be last entry */
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__ETHTOOL_LINK_MODE_MASK_NBITS
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};
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#define __ETHTOOL_LINK_MODE_LEGACY_MASK(base_name) \
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@ -1569,12 +1593,13 @@ enum ethtool_link_mode_bit_indices {
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#define SPEED_50000 50000
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#define SPEED_56000 56000
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#define SPEED_100000 100000
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#define SPEED_200000 200000
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#define SPEED_UNKNOWN -1
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static inline int ethtool_validate_speed(uint32_t speed)
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{
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return speed <= INT_MAX || speed == SPEED_UNKNOWN;
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return speed <= INT_MAX || speed == (uint32_t)SPEED_UNKNOWN;
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}
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/* Duplex, half or full. */
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@ -1687,6 +1712,9 @@ static inline int ethtool_validate_duplex(uint8_t duplex)
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#define ETH_MODULE_SFF_8436 0x4
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#define ETH_MODULE_SFF_8436_LEN 256
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#define ETH_MODULE_SFF_8636_MAX_LEN 640
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#define ETH_MODULE_SFF_8436_MAX_LEN 640
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/* Reset flags */
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/* The reset() operation must clear the flags for the components which
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* were actually reset. On successful return, the flags indicate the
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@ -439,10 +439,12 @@
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#define KEY_TITLE 0x171
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#define KEY_SUBTITLE 0x172
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#define KEY_ANGLE 0x173
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#define KEY_ZOOM 0x174
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#define KEY_FULL_SCREEN 0x174 /* AC View Toggle */
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#define KEY_ZOOM KEY_FULL_SCREEN
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#define KEY_MODE 0x175
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#define KEY_KEYBOARD 0x176
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#define KEY_SCREEN 0x177
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#define KEY_ASPECT_RATIO 0x177 /* HUTRR37: Aspect */
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#define KEY_SCREEN KEY_ASPECT_RATIO
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#define KEY_PC 0x178 /* Media Select Computer */
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#define KEY_TV 0x179 /* Media Select TV */
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#define KEY_TV2 0x17a /* Media Select Cable */
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@ -604,6 +606,7 @@
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#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */
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#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */
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#define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */
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#define KEY_KBD_LAYOUT_NEXT 0x248 /* AC Next Keyboard Layout Select */
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#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */
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#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */
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@ -716,6 +719,8 @@
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* the situation described above.
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*/
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#define REL_RESERVED 0x0a
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#define REL_WHEEL_HI_RES 0x0b
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#define REL_HWHEEL_HI_RES 0x0c
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#define REL_MAX 0x0f
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#define REL_CNT (REL_MAX+1)
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@ -23,13 +23,17 @@
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*/
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struct input_event {
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#if (HOST_LONG_BITS != 32 || !defined(__USE_TIME_BITS64)) && !defined(__KERNEL)
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#if (HOST_LONG_BITS != 32 || !defined(__USE_TIME_BITS64)) && !defined(__KERNEL__)
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struct timeval time;
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#define input_event_sec time.tv_sec
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#define input_event_usec time.tv_usec
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#else
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unsigned long __sec;
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#if defined(__sparc__) && defined(__arch64__)
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unsigned int __usec;
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#else
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unsigned long __usec;
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#endif
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#define input_event_sec __sec
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#define input_event_usec __usec
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#endif
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@ -1,7 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* pci_regs.h
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*
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* PCI standard defines
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* Copyright 1994, Drew Eckhardt
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* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
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@ -15,7 +13,7 @@
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* PCI System Design Guide
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*
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* For HyperTransport information, please consult the following manuals
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* from http://www.hypertransport.org
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* from http://www.hypertransport.org :
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*
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* The HyperTransport I/O Link Specification
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*/
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@ -301,7 +299,7 @@
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#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
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#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
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/* Message Signalled Interrupts registers */
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/* Message Signalled Interrupt registers */
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#define PCI_MSI_FLAGS 2 /* Message Control */
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#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
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@ -319,7 +317,7 @@
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#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
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#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
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/* MSI-X registers */
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/* MSI-X registers (in MSI-X capability) */
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#define PCI_MSIX_FLAGS 2 /* Message Control */
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#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */
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#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */
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@ -333,13 +331,13 @@
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#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */
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#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
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/* MSI-X Table entry format */
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/* MSI-X Table entry format (in memory mapped by a BAR) */
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#define PCI_MSIX_ENTRY_SIZE 16
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#define PCI_MSIX_ENTRY_LOWER_ADDR 0
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#define PCI_MSIX_ENTRY_UPPER_ADDR 4
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#define PCI_MSIX_ENTRY_DATA 8
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#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
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#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
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#define PCI_MSIX_ENTRY_LOWER_ADDR 0 /* Message Address */
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#define PCI_MSIX_ENTRY_UPPER_ADDR 4 /* Message Upper Address */
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#define PCI_MSIX_ENTRY_DATA 8 /* Message Data */
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#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 /* Vector Control */
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#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001
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/* CompactPCI Hotswap Register */
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@ -372,6 +370,12 @@
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#define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */
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#define PCI_EA_ES 0x00000007 /* Entry Size */
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#define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
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/* EA fixed Secondary and Subordinate bus numbers for Bridge */
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#define PCI_EA_SEC_BUS_MASK 0xff
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#define PCI_EA_SUB_BUS_MASK 0xff00
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#define PCI_EA_SUB_BUS_SHIFT 8
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/* 0-5 map to BARs 0-5 respectively */
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#define PCI_EA_BEI_BAR0 0
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#define PCI_EA_BEI_BAR5 5
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@ -465,19 +469,19 @@
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/* PCI Express capability registers */
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#define PCI_EXP_FLAGS 2 /* Capabilities register */
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#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
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#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
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#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
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#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
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#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
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#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
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#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
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#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
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#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
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#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
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#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
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#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
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#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
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#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
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#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
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#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
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#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
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#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
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#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
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#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
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#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
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#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
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#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
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#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
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#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
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#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
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#define PCI_EXP_DEVCAP 4 /* Device capabilities */
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#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */
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#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */
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@ -616,8 +620,8 @@
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#define PCI_EXP_RTCAP 30 /* Root Capabilities */
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#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
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#define PCI_EXP_RTSTA 32 /* Root Status */
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#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
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#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */
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#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
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#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */
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/*
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* The Device Capabilities 2, Device Status 2, Device Control 2,
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* Link Capabilities 2, Link Status 2, Link Control 2,
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@ -637,13 +641,13 @@
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#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
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#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
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#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
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#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
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#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
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#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
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#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
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#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */
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#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
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#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
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#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
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#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
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#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
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#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
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#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
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@ -659,11 +663,11 @@
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#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
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#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
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#define PCI_EXP_LNKCTL2_TLS 0x000f
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#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
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#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKCTL2_TLS 0x000f
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#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
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#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
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#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
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#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
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@ -752,18 +756,18 @@
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#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
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#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
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#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
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#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
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#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
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#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */
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#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
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#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
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#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */
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#define PCI_ERR_ROOT_STATUS 48
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#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
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#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */
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#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */
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#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */
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#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */
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#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
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#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
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#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
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#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
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#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */
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#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */
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#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */
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#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */
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#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
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#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
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#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
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#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
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/* Virtual Channel */
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@ -866,6 +870,7 @@
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#define PCI_ATS_CAP 0x04 /* ATS Capability Register */
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#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */
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#define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */
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#define PCI_ATS_CAP_PAGE_ALIGNED 0x0020 /* Page Aligned Request */
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#define PCI_ATS_CTRL 0x06 /* ATS Control Register */
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#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
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#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
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@ -874,12 +879,13 @@
|
|||
|
||||
/* Page Request Interface */
|
||||
#define PCI_PRI_CTRL 0x04 /* PRI control register */
|
||||
#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */
|
||||
#define PCI_PRI_CTRL_RESET 0x02 /* Reset */
|
||||
#define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */
|
||||
#define PCI_PRI_CTRL_RESET 0x0002 /* Reset */
|
||||
#define PCI_PRI_STATUS 0x06 /* PRI status register */
|
||||
#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */
|
||||
#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */
|
||||
#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
|
||||
#define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */
|
||||
#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */
|
||||
#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */
|
||||
#define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */
|
||||
#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
|
||||
#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
|
||||
#define PCI_EXT_CAP_PRI_SIZEOF 16
|
||||
|
|
@ -896,16 +902,16 @@
|
|||
|
||||
/* Single Root I/O Virtualization */
|
||||
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
|
||||
#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
|
||||
#define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */
|
||||
#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
|
||||
#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
|
||||
#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
|
||||
#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */
|
||||
#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */
|
||||
#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
|
||||
#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
|
||||
#define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */
|
||||
#define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */
|
||||
#define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */
|
||||
#define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */
|
||||
#define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
|
||||
#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
|
||||
#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */
|
||||
#define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */
|
||||
#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
|
||||
#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
|
||||
#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
|
||||
|
|
@ -935,13 +941,13 @@
|
|||
|
||||
/* Access Control Service */
|
||||
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
|
||||
#define PCI_ACS_SV 0x01 /* Source Validation */
|
||||
#define PCI_ACS_TB 0x02 /* Translation Blocking */
|
||||
#define PCI_ACS_RR 0x04 /* P2P Request Redirect */
|
||||
#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */
|
||||
#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
|
||||
#define PCI_ACS_EC 0x20 /* P2P Egress Control */
|
||||
#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
|
||||
#define PCI_ACS_SV 0x0001 /* Source Validation */
|
||||
#define PCI_ACS_TB 0x0002 /* Translation Blocking */
|
||||
#define PCI_ACS_RR 0x0004 /* P2P Request Redirect */
|
||||
#define PCI_ACS_CR 0x0008 /* P2P Completion Redirect */
|
||||
#define PCI_ACS_UF 0x0010 /* Upstream Forwarding */
|
||||
#define PCI_ACS_EC 0x0020 /* P2P Egress Control */
|
||||
#define PCI_ACS_DT 0x0040 /* Direct Translated P2P */
|
||||
#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
|
||||
#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
|
||||
#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
|
||||
|
|
@ -991,9 +997,9 @@
|
|||
#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
|
||||
|
||||
#define PCI_EXP_DPC_CTL 6 /* DPC control */
|
||||
#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */
|
||||
#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
|
||||
#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
|
||||
#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */
|
||||
#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
|
||||
#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
|
||||
|
||||
#define PCI_EXP_DPC_STATUS 8 /* DPC Status */
|
||||
#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */
|
||||
|
|
|
|||
|
|
@ -78,6 +78,12 @@
|
|||
/* This feature indicates support for the packed virtqueue layout. */
|
||||
#define VIRTIO_F_RING_PACKED 34
|
||||
|
||||
/*
|
||||
* This feature indicates that memory accesses by the driver and the
|
||||
* device are ordered in a way described by the platform.
|
||||
*/
|
||||
#define VIRTIO_F_ORDER_PLATFORM 36
|
||||
|
||||
/*
|
||||
* Does the device support Single Root I/O Virtualization?
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -40,8 +40,16 @@
|
|||
|
||||
#include "standard-headers/linux/types.h"
|
||||
|
||||
#define VIRTIO_GPU_F_VIRGL 0
|
||||
#define VIRTIO_GPU_F_EDID 1
|
||||
/*
|
||||
* VIRTIO_GPU_CMD_CTX_*
|
||||
* VIRTIO_GPU_CMD_*_3D
|
||||
*/
|
||||
#define VIRTIO_GPU_F_VIRGL 0
|
||||
|
||||
/*
|
||||
* VIRTIO_GPU_CMD_GET_EDID
|
||||
*/
|
||||
#define VIRTIO_GPU_F_EDID 1
|
||||
|
||||
enum virtio_gpu_ctrl_type {
|
||||
VIRTIO_GPU_UNDEFINED = 0,
|
||||
|
|
|
|||
|
|
@ -211,14 +211,4 @@ struct vring_packed_desc {
|
|||
uint16_t flags;
|
||||
};
|
||||
|
||||
struct vring_packed {
|
||||
unsigned int num;
|
||||
|
||||
struct vring_packed_desc *desc;
|
||||
|
||||
struct vring_packed_desc_event *driver;
|
||||
|
||||
struct vring_packed_desc_event *device;
|
||||
};
|
||||
|
||||
#endif /* _LINUX_VIRTIO_RING_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue