mirror of
https://github.com/Motorhead1991/qemu.git
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ppc patch queue 2018-02-16
Highlights of this batch:
* Conversion to TranslatorOps (Emilio Cota)
* Further bugfixes and cleanups to vcpu id allocation for pseries
(Greg Kurz)
* Another bugfix for HPT resizing (Daniel Henrique-Barboza)
* Macintosh CUDA cleanups (Mark Cave-Ayland)
* Further tweaks to Spectre/Meltdown mitigations (Suraj Singh)
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180216' into staging
ppc patch queue 2018-02-16
Highlights of this batch:
* Conversion to TranslatorOps (Emilio Cota)
* Further bugfixes and cleanups to vcpu id allocation for pseries
(Greg Kurz)
* Another bugfix for HPT resizing (Daniel Henrique-Barboza)
* Macintosh CUDA cleanups (Mark Cave-Ayland)
* Further tweaks to Spectre/Meltdown mitigations (Suraj Singh)
# gpg: Signature made Fri 16 Feb 2018 10:00:02 GMT
# gpg: using RSA key 6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.12-20180216:
ppc4xx: Add device models found in PPC440 core SoCs
ppc/spapr-caps: Disallow setting workaround for spapr-cap-ibs
target/ppc: convert to TranslatorOps
target/ppc: convert to DisasContextBase
spapr: consolidate the VCPU id numbering logic in a single place
spapr: rename spapr_vcpu_id() to spapr_get_vcpu_id()
spapr: move VCPU calculation to core machine code
spapr: use spapr->vsmt to compute VCPU ids
ppc/spapr-caps: Change migration macro to take full spapr-cap name
hw/char: remove legacy interface escc_init()
hw/ppc/spapr_hcall: set htab_shift after kvmppc_resize_hpt_commit
cuda: convert to trace-events
ppc: move CUDAState and other CUDA-related definitions into separate cuda.h file
cuda: convert to use the shared mos6522 device
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
d9c92ae335
22 changed files with 1964 additions and 982 deletions
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@ -1,14 +1,58 @@
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#ifndef HW_ESCC_H
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#define HW_ESCC_H
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#include "chardev/char-fe.h"
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#include "chardev/char-serial.h"
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#include "ui/input.h"
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/* escc.c */
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#define TYPE_ESCC "escc"
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#define ESCC_SIZE 4
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MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
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Chardev *chrA, Chardev *chrB,
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int clock, int it_shift);
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void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
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int disabled, int clock, int it_shift);
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#define ESCC(obj) OBJECT_CHECK(ESCCState, (obj), TYPE_ESCC)
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typedef enum {
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escc_chn_a, escc_chn_b,
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} ESCCChnID;
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typedef enum {
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escc_serial, escc_kbd, escc_mouse,
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} ESCCChnType;
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#define ESCC_SERIO_QUEUE_SIZE 256
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typedef struct {
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uint8_t data[ESCC_SERIO_QUEUE_SIZE];
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int rptr, wptr, count;
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} ESCCSERIOQueue;
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#define ESCC_SERIAL_REGS 16
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typedef struct ESCCChannelState {
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qemu_irq irq;
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uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
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struct ESCCChannelState *otherchn;
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uint32_t reg;
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uint8_t wregs[ESCC_SERIAL_REGS], rregs[ESCC_SERIAL_REGS];
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ESCCSERIOQueue queue;
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CharBackend chr;
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int e0_mode, led_mode, caps_lock_mode, num_lock_mode;
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int disabled;
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int clock;
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uint32_t vmstate_dummy;
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ESCCChnID chn; /* this channel, A (base+4) or B (base+0) */
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ESCCChnType type;
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uint8_t rx, tx;
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QemuInputHandlerState *hs;
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} ESCCChannelState;
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typedef struct ESCCState {
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SysBusDevice parent_obj;
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struct ESCCChannelState chn[2];
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uint32_t it_shift;
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MemoryRegion mmio;
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uint32_t disabled;
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uint32_t frequency;
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} ESCCState;
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#endif
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107
include/hw/misc/macio/cuda.h
Normal file
107
include/hw/misc/macio/cuda.h
Normal file
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@ -0,0 +1,107 @@
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/*
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* QEMU PowerMac CUDA device support
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef CUDA_H
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#define CUDA_H
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/* CUDA commands (2nd byte) */
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#define CUDA_WARM_START 0x0
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#define CUDA_AUTOPOLL 0x1
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#define CUDA_GET_6805_ADDR 0x2
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#define CUDA_GET_TIME 0x3
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#define CUDA_GET_PRAM 0x7
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#define CUDA_SET_6805_ADDR 0x8
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#define CUDA_SET_TIME 0x9
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#define CUDA_POWERDOWN 0xa
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#define CUDA_POWERUP_TIME 0xb
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#define CUDA_SET_PRAM 0xc
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#define CUDA_MS_RESET 0xd
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#define CUDA_SEND_DFAC 0xe
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#define CUDA_BATTERY_SWAP_SENSE 0x10
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#define CUDA_RESET_SYSTEM 0x11
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#define CUDA_SET_IPL 0x12
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#define CUDA_FILE_SERVER_FLAG 0x13
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#define CUDA_SET_AUTO_RATE 0x14
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#define CUDA_GET_AUTO_RATE 0x16
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#define CUDA_SET_DEVICE_LIST 0x19
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#define CUDA_GET_DEVICE_LIST 0x1a
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#define CUDA_SET_ONE_SECOND_MODE 0x1b
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#define CUDA_SET_POWER_MESSAGES 0x21
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#define CUDA_GET_SET_IIC 0x22
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#define CUDA_WAKEUP 0x23
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#define CUDA_TIMER_TICKLE 0x24
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#define CUDA_COMBINED_FORMAT_IIC 0x25
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/* Cuda */
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#define TYPE_CUDA "cuda"
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#define CUDA(obj) OBJECT_CHECK(CUDAState, (obj), TYPE_CUDA)
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typedef struct MOS6522CUDAState MOS6522CUDAState;
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typedef struct CUDAState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mem;
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ADBBusState adb_bus;
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MOS6522CUDAState *mos6522_cuda;
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uint32_t tick_offset;
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uint64_t tb_frequency;
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uint8_t last_b;
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uint8_t last_acr;
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/* MacOS 9 is racy and requires a delay upon setting the SR_INT bit */
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uint64_t sr_delay_ns;
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QEMUTimer *sr_delay_timer;
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int data_in_size;
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int data_in_index;
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int data_out_index;
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qemu_irq irq;
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uint16_t adb_poll_mask;
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uint8_t autopoll_rate_ms;
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uint8_t autopoll;
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uint8_t data_in[128];
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uint8_t data_out[16];
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QEMUTimer *adb_poll_timer;
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} CUDAState;
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/* MOS6522 CUDA */
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typedef struct MOS6522CUDAState {
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/*< private >*/
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MOS6522State parent_obj;
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CUDAState *cuda;
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} MOS6522CUDAState;
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#define TYPE_MOS6522_CUDA "mos6522-cuda"
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#define MOS6522_CUDA(obj) OBJECT_CHECK(MOS6522CUDAState, (obj), \
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TYPE_MOS6522_CUDA)
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#endif /* CUDA_H */
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* bit 12 - 14: function number
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* bit 0 - 11: offset in configuration space of a given device
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*/
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#define PCIE_MMCFG_SIZE_MAX (1ULL << 28)
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#define PCIE_MMCFG_SIZE_MAX (1ULL << 29)
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#define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
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#define PCIE_MMCFG_BUS_BIT 20
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#define PCIE_MMCFG_BUS_MASK 0x1ff
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@ -766,7 +766,8 @@ void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
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#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
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int spapr_vcpu_id(PowerPCCPU *cpu);
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int spapr_get_vcpu_id(PowerPCCPU *cpu);
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void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
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PowerPCCPU *spapr_find_cpu(int vcpu_id);
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int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi,
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