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Make it safe to use 64 bits GPR and/or 64 bits host registers.

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For "symetry", add 64 bits versions of all modified functions.
As a side effect, add a lot of code provision for PowerPC 64 support.
Move overflow and carry checks in common routines for simple cases.
Add isel and popcntb instructions from PowerPC 2.03 specification.
Remove remaining micro-operations helpers prototypes from op.c.
Fix XER_BC field to be 7 bits long.
Add power management support for PowerPC 603 & 604.
Fix compilation warnings.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2482 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-03-17 14:02:15 +00:00
parent 5fd46862e5
commit d9bce9d99f
9 changed files with 3045 additions and 639 deletions
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22
target-ppc/exec.h
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@ -34,19 +34,25 @@ register struct CPUPPCState *env asm(AREG0);
#define T1 (env->t1)
#define T2 (env->t2)
#else
/* This may be more efficient if HOST_LONG_BITS > TARGET_LONG_BITS
* To be set to one when we'll be sure it does not cause bugs....
*/
#if 0
register unsigned long T0 asm(AREG1);
register unsigned long T1 asm(AREG2);
register unsigned long T2 asm(AREG3);
#endif
/* We may, sometime, need 64 bits registers on 32 bits target */
#if defined(TARGET_PPC64) || (HOST_LONG_BITS == 64)
#define T0_64 T0
#define T1_64 T0
#define T2_64 T0
#else
register target_ulong T0 asm(AREG1);
register target_ulong T1 asm(AREG2);
register target_ulong T2 asm(AREG3);
#endif
/* no registers can be used */
#define T0_64 (env->t0)
#define T1_64 (env->t1)
#define T2_64 (env->t2)
#endif
/* Provision for Altivec */
#define T0_avr (env->t0_avr)
#define T1_avr (env->t1_avr)
#define T2_avr (env->t2_avr)
/* XXX: to clean: remove this mess */
#define PARAM(n) ((uint32_t)PARAM##n)