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tcg/arm: Drop addrhi from prepare_host_addr
The guest address will now always be TCG_TYPE_I32. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
50b7a197e1
commit
d9a8889f6d
1 changed files with 23 additions and 50 deletions
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@ -676,14 +676,8 @@ static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt,
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tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0);
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}
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static void __attribute__((unused))
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tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm)
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{
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tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1);
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}
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static void __attribute__((unused))
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tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8)
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static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt,
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TCGReg rn, int imm8)
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{
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tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0);
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}
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@ -1455,8 +1449,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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#define MIN_TLB_MASK_TABLE_OFS -256
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static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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TCGReg addrlo, TCGReg addrhi,
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MemOpIdx oi, bool is_ld)
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TCGReg addr, MemOpIdx oi, bool is_ld)
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{
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TCGLabelQemuLdst *ldst = NULL;
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MemOp opc = get_memop(oi);
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@ -1465,14 +1458,14 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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if (tcg_use_softmmu) {
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*h = (HostAddress){
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.cond = COND_AL,
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.base = addrlo,
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.base = addr,
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.index = TCG_REG_R1,
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.index_scratch = true,
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};
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} else {
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*h = (HostAddress){
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.cond = COND_AL,
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.base = addrlo,
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.base = addr,
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.index = guest_base ? TCG_REG_GUEST_BASE : -1,
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.index_scratch = false,
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};
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@ -1492,8 +1485,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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ldst->addrlo_reg = addr;
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/* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
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@ -1501,30 +1493,20 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
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/* Extract the tlb index from the address into R0. */
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tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
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tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr,
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SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS));
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/*
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* Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
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* Load the tlb comparator into R2/R3 and the fast path addend into R1.
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* Load the tlb comparator into R2 and the fast path addend into R1.
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*/
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QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
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if (cmp_off == 0) {
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if (s->addr_type == TCG_TYPE_I32) {
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tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2,
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TCG_REG_R1, TCG_REG_R0);
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} else {
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tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2,
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TCG_REG_R1, TCG_REG_R0);
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}
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tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
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} else {
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
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TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
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if (s->addr_type == TCG_TYPE_I32) {
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
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} else {
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
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}
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
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}
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/* Load the tlb addend. */
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@ -1543,11 +1525,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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* This leaves the least significant alignment bits unchanged, and of
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* course must be zero.
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*/
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t_addr = addrlo;
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t_addr = addr;
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if (a_mask < s_mask) {
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t_addr = TCG_REG_R0;
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr,
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addrlo, s_mask - a_mask);
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addr, s_mask - a_mask);
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}
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if (use_armv7_instructions && s->page_bits <= 16) {
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tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask));
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@ -1558,7 +1540,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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} else {
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if (a_mask) {
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tcg_debug_assert(a_mask <= 0xff);
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask);
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}
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr,
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SHIFT_IMM_LSR(s->page_bits));
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@ -1566,21 +1548,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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0, TCG_REG_R2, TCG_REG_TMP,
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SHIFT_IMM_LSL(s->page_bits));
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}
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if (s->addr_type != TCG_TYPE_I32) {
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tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
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}
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} else if (a_mask) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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ldst->addrlo_reg = addr;
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/* We are expecting alignment to max out at 7 */
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tcg_debug_assert(a_mask <= 0xff);
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/* tst addr, #mask */
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask);
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}
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return ldst;
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@ -1678,14 +1655,13 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
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}
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static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addrhi,
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MemOpIdx oi, TCGType data_type)
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TCGReg addr, MemOpIdx oi, TCGType data_type)
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{
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MemOp opc = get_memop(oi);
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TCGLabelQemuLdst *ldst;
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HostAddress h;
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ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
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ldst = prepare_host_addr(s, &h, addr, oi, true);
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if (ldst) {
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ldst->type = data_type;
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ldst->datalo_reg = datalo;
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@ -1764,14 +1740,13 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
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}
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static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addrhi,
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MemOpIdx oi, TCGType data_type)
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TCGReg addr, MemOpIdx oi, TCGType data_type)
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{
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MemOp opc = get_memop(oi);
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TCGLabelQemuLdst *ldst;
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HostAddress h;
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ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
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ldst = prepare_host_addr(s, &h, addr, oi, false);
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if (ldst) {
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ldst->type = data_type;
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ldst->datalo_reg = datalo;
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@ -2072,19 +2047,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
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break;
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case INDEX_op_qemu_ld_i32:
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tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
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tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
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break;
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case INDEX_op_qemu_ld_i64:
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tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
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args[3], TCG_TYPE_I64);
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tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64);
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break;
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case INDEX_op_qemu_st_i32:
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tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
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tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
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break;
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case INDEX_op_qemu_st_i64:
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tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
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args[3], TCG_TYPE_I64);
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tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64);
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break;
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case INDEX_op_bswap16_i32:
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