mirror of
https://github.com/Motorhead1991/qemu.git
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include/qemu: Tidy atomic128 headers.
include/exec: Split out cpu-interrupt.h include/exec: Split many tlb_* declarations to cputlb.h include/accel/tcg: Split out getpc.h accel/tcg: system: Compile some files once linux-user/main: Allow setting tb-size -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmfMyz8dHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9D/Af/Vh5PMtYjL+Mw2NQn Vmqbv+joiqswAxI8PmZZzEBJ06j4pCLXn+r/2nr+sEwLmrI4BI40Vxx5c5puftoZ GDGGclskF/pId5TE96TCEr8AoJgeNSSv4WxbINFTZRsRP4voZFHpU6mTz6B0Nnq5 GS/k6c7+VcYbHIPD0RcIWwBlQv11uUAcnaygkNSsy+theUseOzTPTN/XGfTprf/6 1sxlmtt6QcQ88bBJJbiNwqbjWGxANcSUspRo0sstpVr8ApkXNl7WSkWYRBhBa5oc iu0tixdCIoqqcCJy9/YVyIkmmwWeRUkbQqBeKf0o5xPnhmO3kfeezvERSDvDViAH K9BVBw== =7vra -----END PGP SIGNATURE----- Merge tag 'pull-tcg-20250308' of https://gitlab.com/rth7680/qemu into staging include/qemu: Tidy atomic128 headers. include/exec: Split out cpu-interrupt.h include/exec: Split many tlb_* declarations to cputlb.h include/accel/tcg: Split out getpc.h accel/tcg: system: Compile some files once linux-user/main: Allow setting tb-size # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmfMyz8dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9D/Af/Vh5PMtYjL+Mw2NQn # Vmqbv+joiqswAxI8PmZZzEBJ06j4pCLXn+r/2nr+sEwLmrI4BI40Vxx5c5puftoZ # GDGGclskF/pId5TE96TCEr8AoJgeNSSv4WxbINFTZRsRP4voZFHpU6mTz6B0Nnq5 # GS/k6c7+VcYbHIPD0RcIWwBlQv11uUAcnaygkNSsy+theUseOzTPTN/XGfTprf/6 # 1sxlmtt6QcQ88bBJJbiNwqbjWGxANcSUspRo0sstpVr8ApkXNl7WSkWYRBhBa5oc # iu0tixdCIoqqcCJy9/YVyIkmmwWeRUkbQqBeKf0o5xPnhmO3kfeezvERSDvDViAH # K9BVBw== # =7vra # -----END PGP SIGNATURE----- # gpg: Signature made Sun 09 Mar 2025 06:57:03 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250308' of https://gitlab.com/rth7680/qemu: (23 commits) accel/tcg: Build tcg-runtime-gvec.c once accel/tcg: Build tcg-runtime.c once qemu/atomic128: Include missing 'qemu/atomic.h' header qemu/atomic: Rename atomic128-ldst.h headers using .h.inc suffix qemu/atomic: Rename atomic128-cas.h headers using .h.inc suffix accel/tcg: Split out getpc.h accel/tcg: Restrict GETPC_ADJ to 'tb-internal.h' accel/tcg: Build tcg-accel-ops-mttcg.c once accel/tcg: Build tcg-accel-ops-rr.c once accel/tcg: Build tcg-accel-ops-icount.c once accel/tcg: Build tcg-accel-ops.c once system: Build watchpoint.c once exec: Declare tlb_flush*() in 'exec/cputlb.h' exec: Declare tlb_hit*() in 'exec/cputlb.h' exec: Declare tlb_set_page() in 'exec/cputlb.h' exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h' exec: Declare tlb_set_page_full() in 'exec/cputlb.h' exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h' accel/tcg: Compile watchpoint.c once include/exec: Split out exec/cpu-interrupt.h ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
d9a4282c4b
80 changed files with 552 additions and 486 deletions
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@ -21,6 +21,7 @@
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#include "exec/page-protection.h"
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#include "exec/cpu-common.h"
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#include "exec/cpu-interrupt.h"
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#include "exec/memory.h"
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#include "exec/tswap.h"
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#include "hw/core/cpu.h"
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@ -105,81 +106,10 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
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/* page related stuff */
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#include "exec/cpu-defs.h"
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#ifdef TARGET_PAGE_BITS_VARY
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# include "exec/page-vary.h"
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extern const TargetPageBits target_page;
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# ifdef CONFIG_DEBUG_TCG
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# define TARGET_PAGE_BITS ({ assert(target_page.decided); \
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target_page.bits; })
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# define TARGET_PAGE_MASK ({ assert(target_page.decided); \
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(target_long)target_page.mask; })
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# else
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# define TARGET_PAGE_BITS target_page.bits
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# define TARGET_PAGE_MASK ((target_long)target_page.mask)
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# endif
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# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
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#else
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# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
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# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
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# define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
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#endif
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#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
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#include "exec/target_page.h"
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CPUArchState *cpu_copy(CPUArchState *env);
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/* Flags for use in ENV->INTERRUPT_PENDING.
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The numbers assigned here are non-sequential in order to preserve
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binary compatibility with the vmstate dump. Bit 0 (0x0001) was
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previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
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the vmstate dump. */
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/* External hardware interrupt pending. This is typically used for
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interrupts from devices. */
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#define CPU_INTERRUPT_HARD 0x0002
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/* Exit the current TB. This is typically used when some system-level device
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makes some change to the memory mapping. E.g. the a20 line change. */
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#define CPU_INTERRUPT_EXITTB 0x0004
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/* Halt the CPU. */
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#define CPU_INTERRUPT_HALT 0x0020
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/* Debug event pending. */
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#define CPU_INTERRUPT_DEBUG 0x0080
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/* Reset signal. */
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#define CPU_INTERRUPT_RESET 0x0400
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/* Several target-specific external hardware interrupts. Each target/cpu.h
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should define proper names based on these defines. */
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#define CPU_INTERRUPT_TGT_EXT_0 0x0008
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#define CPU_INTERRUPT_TGT_EXT_1 0x0010
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#define CPU_INTERRUPT_TGT_EXT_2 0x0040
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#define CPU_INTERRUPT_TGT_EXT_3 0x0200
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#define CPU_INTERRUPT_TGT_EXT_4 0x1000
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/* Several target-specific internal interrupts. These differ from the
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preceding target-specific interrupts in that they are intended to
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originate from within the cpu itself, typically in response to some
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instruction being executed. These, therefore, are not masked while
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single-stepping within the debugger. */
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#define CPU_INTERRUPT_TGT_INT_0 0x0100
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#define CPU_INTERRUPT_TGT_INT_1 0x0800
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#define CPU_INTERRUPT_TGT_INT_2 0x2000
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/* First unused bit: 0x4000. */
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/* The set of all bits that should be masked when single-stepping. */
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#define CPU_INTERRUPT_SSTEP_MASK \
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(CPU_INTERRUPT_HARD \
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| CPU_INTERRUPT_TGT_EXT_0 \
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| CPU_INTERRUPT_TGT_EXT_1 \
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| CPU_INTERRUPT_TGT_EXT_2 \
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| CPU_INTERRUPT_TGT_EXT_3 \
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| CPU_INTERRUPT_TGT_EXT_4)
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#include "cpu.h"
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#ifdef CONFIG_USER_ONLY
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@ -249,29 +179,6 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
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/* The two sets of flags must not overlap. */
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QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
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/**
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* tlb_hit_page: return true if page aligned @addr is a hit against the
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* TLB entry @tlb_addr
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*
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* @addr: virtual address to test (must be page aligned)
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* @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
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*/
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static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
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{
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return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
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}
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/**
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* tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
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*
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* @addr: virtual address to test (need not be page aligned)
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* @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
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*/
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static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
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{
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return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
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}
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#endif /* !CONFIG_USER_ONLY */
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/* Validate correct placement of CPUArchState. */
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@ -46,30 +46,4 @@
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#include "exec/target_long.h"
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#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
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#define CPU_TLB_DYN_MIN_BITS 6
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#define CPU_TLB_DYN_DEFAULT_BITS 8
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# if HOST_LONG_BITS == 32
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/* Make sure we do not require a double-word shift for the TLB load */
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# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
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# else /* HOST_LONG_BITS == 64 */
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/*
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* Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
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* 2**34 == 16G of address space. This is roughly what one would expect a
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* TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
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* Skylake's Level-2 STLB has 16 1G entries.
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* Also, make sure we do not size the TLB past the guest's address space.
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*/
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# ifdef TARGET_PAGE_BITS_VARY
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# define CPU_TLB_DYN_MAX_BITS \
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MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
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# else
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# define CPU_TLB_DYN_MAX_BITS \
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MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
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# endif
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# endif
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#endif /* CONFIG_SOFTMMU && CONFIG_TCG */
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#endif
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70
include/exec/cpu-interrupt.h
Normal file
70
include/exec/cpu-interrupt.h
Normal file
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@ -0,0 +1,70 @@
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/*
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* Flags for use with cpu_interrupt()
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*
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* Copyright (c) 2003 Fabrice Bellard
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#ifndef CPU_INTERRUPT_H
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#define CPU_INTERRUPT_H
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/*
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* The numbers assigned here are non-sequential in order to preserve binary
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* compatibility with the vmstate dump. Bit 0 (0x0001) was previously used
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* for CPU_INTERRUPT_EXIT, and is cleared when loading the vmstate dump.
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*/
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/*
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* External hardware interrupt pending.
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* This is typically used for interrupts from devices.
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*/
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#define CPU_INTERRUPT_HARD 0x0002
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/*
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* Exit the current TB. This is typically used when some system-level device
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* makes some change to the memory mapping. E.g. the a20 line change.
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*/
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#define CPU_INTERRUPT_EXITTB 0x0004
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/* Halt the CPU. */
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#define CPU_INTERRUPT_HALT 0x0020
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/* Debug event pending. */
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#define CPU_INTERRUPT_DEBUG 0x0080
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/* Reset signal. */
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#define CPU_INTERRUPT_RESET 0x0400
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/*
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* Several target-specific external hardware interrupts. Each target/cpu.h
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* should define proper names based on these defines.
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*/
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#define CPU_INTERRUPT_TGT_EXT_0 0x0008
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#define CPU_INTERRUPT_TGT_EXT_1 0x0010
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#define CPU_INTERRUPT_TGT_EXT_2 0x0040
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#define CPU_INTERRUPT_TGT_EXT_3 0x0200
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#define CPU_INTERRUPT_TGT_EXT_4 0x1000
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/*
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* Several target-specific internal interrupts. These differ from the
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* preceding target-specific interrupts in that they are intended to
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* originate from within the cpu itself, typically in response to some
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* instruction being executed. These, therefore, are not masked while
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* single-stepping within the debugger.
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*/
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#define CPU_INTERRUPT_TGT_INT_0 0x0100
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#define CPU_INTERRUPT_TGT_INT_1 0x0800
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#define CPU_INTERRUPT_TGT_INT_2 0x2000
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/* First unused bit: 0x4000. */
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/* The set of all bits that should be masked when single-stepping. */
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#define CPU_INTERRUPT_SSTEP_MASK \
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(CPU_INTERRUPT_HARD \
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| CPU_INTERRUPT_TGT_EXT_0 \
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| CPU_INTERRUPT_TGT_EXT_1 \
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| CPU_INTERRUPT_TGT_EXT_2 \
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| CPU_INTERRUPT_TGT_EXT_3 \
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| CPU_INTERRUPT_TGT_EXT_4)
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#endif /* CPU_INTERRUPT_H */
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@ -21,15 +21,266 @@
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#define CPUTLB_H
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#include "exec/cpu-common.h"
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#include "exec/hwaddr.h"
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#include "exec/memattrs.h"
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#include "exec/vaddr.h"
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#ifdef CONFIG_TCG
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#if !defined(CONFIG_USER_ONLY)
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/* cputlb.c */
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#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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void tlb_protect_code(ram_addr_t ram_addr);
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void tlb_unprotect_code(ram_addr_t ram_addr);
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#endif
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#endif /* CONFIG_TCG */
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#ifndef CONFIG_USER_ONLY
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void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
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void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
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#endif
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/**
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* tlb_set_page_full:
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* @cpu: CPU context
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* @mmu_idx: mmu index of the tlb to modify
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* @addr: virtual address of the entry to add
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* @full: the details of the tlb entry
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*
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* Add an entry to @cpu tlb index @mmu_idx. All of the fields of
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* @full must be filled, except for xlat_section, and constitute
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* the complete description of the translated page.
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*
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* This is generally called by the target tlb_fill function after
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* having performed a successful page table walk to find the physical
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* address and attributes for the translation.
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*
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* At most one entry for a given virtual address is permitted. Only a
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* single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
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* used by tlb_flush_page.
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*/
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void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
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CPUTLBEntryFull *full);
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/**
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* tlb_set_page_with_attrs:
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* @cpu: CPU to add this TLB entry for
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* @addr: virtual address of page to add entry for
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* @paddr: physical address of the page
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* @attrs: memory transaction attributes
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* @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
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* @mmu_idx: MMU index to insert TLB entry for
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* @size: size of the page in bytes
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*
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* Add an entry to this CPU's TLB (a mapping from virtual address
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* @addr to physical address @paddr) with the specified memory
|
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* transaction attributes. This is generally called by the target CPU
|
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* specific code after it has been called through the tlb_fill()
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* entry point and performed a successful page table walk to find
|
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* the physical address and attributes for the virtual address
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* which provoked the TLB miss.
|
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*
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* At most one entry for a given virtual address is permitted. Only a
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* single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
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* used by tlb_flush_page.
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*/
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void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
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hwaddr paddr, MemTxAttrs attrs,
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int prot, int mmu_idx, vaddr size);
|
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|
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/**
|
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* tlb_set_page:
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*
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* This function is equivalent to calling tlb_set_page_with_attrs()
|
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* with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
|
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* as a convenience for CPUs which don't use memory transaction attributes.
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*/
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void tlb_set_page(CPUState *cpu, vaddr addr,
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hwaddr paddr, int prot,
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int mmu_idx, vaddr size);
|
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|
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#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
|
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/**
|
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* tlb_flush_page:
|
||||
* @cpu: CPU whose TLB should be flushed
|
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* @addr: virtual address of page to be flushed
|
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*
|
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* Flush one page from the TLB of the specified CPU, for all
|
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* MMU indexes.
|
||||
*/
|
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void tlb_flush_page(CPUState *cpu, vaddr addr);
|
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|
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/**
|
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* tlb_flush_page_all_cpus_synced:
|
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* @cpu: src CPU of the flush
|
||||
* @addr: virtual address of page to be flushed
|
||||
*
|
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* Flush one page from the TLB of all CPUs, for all
|
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* MMU indexes.
|
||||
*
|
||||
* When this function returns, no CPUs will subsequently perform
|
||||
* translations using the flushed TLBs.
|
||||
*/
|
||||
void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
|
||||
|
||||
/**
|
||||
* tlb_flush:
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
*
|
||||
* Flush the entire TLB for the specified CPU. Most CPU architectures
|
||||
* allow the implementation to drop entries from the TLB at any time
|
||||
* so this is generally safe. If more selective flushing is required
|
||||
* use one of the other functions for efficiency.
|
||||
*/
|
||||
void tlb_flush(CPUState *cpu);
|
||||
|
||||
/**
|
||||
* tlb_flush_all_cpus_synced:
|
||||
* @cpu: src CPU of the flush
|
||||
*
|
||||
* Flush the entire TLB for all CPUs, for all MMU indexes.
|
||||
*
|
||||
* When this function returns, no CPUs will subsequently perform
|
||||
* translations using the flushed TLBs.
|
||||
*/
|
||||
void tlb_flush_all_cpus_synced(CPUState *src_cpu);
|
||||
|
||||
/**
|
||||
* tlb_flush_page_by_mmuidx:
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
* @addr: virtual address of page to be flushed
|
||||
* @idxmap: bitmap of MMU indexes to flush
|
||||
*
|
||||
* Flush one page from the TLB of the specified CPU, for the specified
|
||||
* MMU indexes.
|
||||
*/
|
||||
void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
|
||||
uint16_t idxmap);
|
||||
|
||||
/**
|
||||
* tlb_flush_page_by_mmuidx_all_cpus_synced:
|
||||
* @cpu: Originating CPU of the flush
|
||||
* @addr: virtual address of page to be flushed
|
||||
* @idxmap: bitmap of MMU indexes to flush
|
||||
*
|
||||
* Flush one page from the TLB of all CPUs, for the specified
|
||||
* MMU indexes.
|
||||
*
|
||||
* When this function returns, no CPUs will subsequently perform
|
||||
* translations using the flushed TLBs.
|
||||
*/
|
||||
void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
|
||||
uint16_t idxmap);
|
||||
|
||||
/**
|
||||
* tlb_flush_by_mmuidx:
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
* @wait: If true ensure synchronisation by exiting the cpu_loop
|
||||
* @idxmap: bitmap of MMU indexes to flush
|
||||
*
|
||||
* Flush all entries from the TLB of the specified CPU, for the specified
|
||||
* MMU indexes.
|
||||
*/
|
||||
void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
|
||||
|
||||
/**
|
||||
* tlb_flush_by_mmuidx_all_cpus_synced:
|
||||
* @cpu: Originating CPU of the flush
|
||||
* @idxmap: bitmap of MMU indexes to flush
|
||||
*
|
||||
* Flush all entries from the TLB of all CPUs, for the specified
|
||||
* MMU indexes.
|
||||
*
|
||||
* When this function returns, no CPUs will subsequently perform
|
||||
* translations using the flushed TLBs.
|
||||
*/
|
||||
void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
|
||||
|
||||
/**
|
||||
* tlb_flush_page_bits_by_mmuidx
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
* @addr: virtual address of page to be flushed
|
||||
* @idxmap: bitmap of mmu indexes to flush
|
||||
* @bits: number of significant bits in address
|
||||
*
|
||||
* Similar to tlb_flush_page_mask, but with a bitmap of indexes.
|
||||
*/
|
||||
void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
|
||||
uint16_t idxmap, unsigned bits);
|
||||
|
||||
/* Similarly, with broadcast and syncing. */
|
||||
void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
|
||||
uint16_t idxmap,
|
||||
unsigned bits);
|
||||
|
||||
/**
|
||||
* tlb_flush_range_by_mmuidx
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
* @addr: virtual address of the start of the range to be flushed
|
||||
* @len: length of range to be flushed
|
||||
* @idxmap: bitmap of mmu indexes to flush
|
||||
* @bits: number of significant bits in address
|
||||
*
|
||||
* For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
|
||||
* comparing only the low @bits worth of each virtual page.
|
||||
*/
|
||||
void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
|
||||
vaddr len, uint16_t idxmap,
|
||||
unsigned bits);
|
||||
|
||||
/* Similarly, with broadcast and syncing. */
|
||||
void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
||||
vaddr addr,
|
||||
vaddr len,
|
||||
uint16_t idxmap,
|
||||
unsigned bits);
|
||||
#else
|
||||
static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush(CPUState *cpu)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
|
||||
vaddr addr, uint16_t idxmap)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
||||
vaddr addr,
|
||||
uint16_t idxmap)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
||||
uint16_t idxmap)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
|
||||
vaddr addr,
|
||||
uint16_t idxmap,
|
||||
unsigned bits)
|
||||
{
|
||||
}
|
||||
static inline void
|
||||
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
|
||||
uint16_t idxmap, unsigned bits)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
|
||||
vaddr len, uint16_t idxmap,
|
||||
unsigned bits)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
||||
vaddr addr,
|
||||
vaddr len,
|
||||
uint16_t idxmap,
|
||||
unsigned bits)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
|
||||
#endif /* CPUTLB_H */
|
||||
|
|
|
|||
|
|
@ -27,247 +27,8 @@
|
|||
#include "exec/mmu-access-type.h"
|
||||
#include "exec/translation-block.h"
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
|
||||
/* cputlb.c */
|
||||
/**
|
||||
* tlb_flush_page:
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
* @addr: virtual address of page to be flushed
|
||||
*
|
||||
* Flush one page from the TLB of the specified CPU, for all
|
||||
* MMU indexes.
|
||||
*/
|
||||
void tlb_flush_page(CPUState *cpu, vaddr addr);
|
||||
/**
|
||||
* tlb_flush_page_all_cpus_synced:
|
||||
* @cpu: src CPU of the flush
|
||||
* @addr: virtual address of page to be flushed
|
||||
*
|
||||
* Flush one page from the TLB of all CPUs, for all
|
||||
* MMU indexes.
|
||||
*
|
||||
* When this function returns, no CPUs will subsequently perform
|
||||
* translations using the flushed TLBs.
|
||||
*/
|
||||
void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
|
||||
/**
|
||||
* tlb_flush:
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
*
|
||||
* Flush the entire TLB for the specified CPU. Most CPU architectures
|
||||
* allow the implementation to drop entries from the TLB at any time
|
||||
* so this is generally safe. If more selective flushing is required
|
||||
* use one of the other functions for efficiency.
|
||||
*/
|
||||
void tlb_flush(CPUState *cpu);
|
||||
/**
|
||||
* tlb_flush_all_cpus_synced:
|
||||
* @cpu: src CPU of the flush
|
||||
*
|
||||
* Flush the entire TLB for all CPUs, for all MMU indexes.
|
||||
*
|
||||
* When this function returns, no CPUs will subsequently perform
|
||||
* translations using the flushed TLBs.
|
||||
*/
|
||||
void tlb_flush_all_cpus_synced(CPUState *src_cpu);
|
||||
/**
|
||||
* tlb_flush_page_by_mmuidx:
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
* @addr: virtual address of page to be flushed
|
||||
* @idxmap: bitmap of MMU indexes to flush
|
||||
*
|
||||
* Flush one page from the TLB of the specified CPU, for the specified
|
||||
* MMU indexes.
|
||||
*/
|
||||
void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
|
||||
uint16_t idxmap);
|
||||
/**
|
||||
* tlb_flush_page_by_mmuidx_all_cpus_synced:
|
||||
* @cpu: Originating CPU of the flush
|
||||
* @addr: virtual address of page to be flushed
|
||||
* @idxmap: bitmap of MMU indexes to flush
|
||||
*
|
||||
* Flush one page from the TLB of all CPUs, for the specified
|
||||
* MMU indexes.
|
||||
*
|
||||
* When this function returns, no CPUs will subsequently perform
|
||||
* translations using the flushed TLBs.
|
||||
*/
|
||||
void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
|
||||
uint16_t idxmap);
|
||||
/**
|
||||
* tlb_flush_by_mmuidx:
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
* @wait: If true ensure synchronisation by exiting the cpu_loop
|
||||
* @idxmap: bitmap of MMU indexes to flush
|
||||
*
|
||||
* Flush all entries from the TLB of the specified CPU, for the specified
|
||||
* MMU indexes.
|
||||
*/
|
||||
void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
|
||||
/**
|
||||
* tlb_flush_by_mmuidx_all_cpus_synced:
|
||||
* @cpu: Originating CPU of the flush
|
||||
* @idxmap: bitmap of MMU indexes to flush
|
||||
*
|
||||
* Flush all entries from the TLB of all CPUs, for the specified
|
||||
* MMU indexes.
|
||||
*
|
||||
* When this function returns, no CPUs will subsequently perform
|
||||
* translations using the flushed TLBs.
|
||||
*/
|
||||
void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
|
||||
|
||||
/**
|
||||
* tlb_flush_page_bits_by_mmuidx
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
* @addr: virtual address of page to be flushed
|
||||
* @idxmap: bitmap of mmu indexes to flush
|
||||
* @bits: number of significant bits in address
|
||||
*
|
||||
* Similar to tlb_flush_page_mask, but with a bitmap of indexes.
|
||||
*/
|
||||
void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
|
||||
uint16_t idxmap, unsigned bits);
|
||||
|
||||
/* Similarly, with broadcast and syncing. */
|
||||
void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
|
||||
(CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits);
|
||||
|
||||
/**
|
||||
* tlb_flush_range_by_mmuidx
|
||||
* @cpu: CPU whose TLB should be flushed
|
||||
* @addr: virtual address of the start of the range to be flushed
|
||||
* @len: length of range to be flushed
|
||||
* @idxmap: bitmap of mmu indexes to flush
|
||||
* @bits: number of significant bits in address
|
||||
*
|
||||
* For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
|
||||
* comparing only the low @bits worth of each virtual page.
|
||||
*/
|
||||
void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
|
||||
vaddr len, uint16_t idxmap,
|
||||
unsigned bits);
|
||||
|
||||
/* Similarly, with broadcast and syncing. */
|
||||
void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
||||
vaddr addr,
|
||||
vaddr len,
|
||||
uint16_t idxmap,
|
||||
unsigned bits);
|
||||
|
||||
/**
|
||||
* tlb_set_page_full:
|
||||
* @cpu: CPU context
|
||||
* @mmu_idx: mmu index of the tlb to modify
|
||||
* @addr: virtual address of the entry to add
|
||||
* @full: the details of the tlb entry
|
||||
*
|
||||
* Add an entry to @cpu tlb index @mmu_idx. All of the fields of
|
||||
* @full must be filled, except for xlat_section, and constitute
|
||||
* the complete description of the translated page.
|
||||
*
|
||||
* This is generally called by the target tlb_fill function after
|
||||
* having performed a successful page table walk to find the physical
|
||||
* address and attributes for the translation.
|
||||
*
|
||||
* At most one entry for a given virtual address is permitted. Only a
|
||||
* single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
|
||||
* used by tlb_flush_page.
|
||||
*/
|
||||
void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
|
||||
CPUTLBEntryFull *full);
|
||||
|
||||
/**
|
||||
* tlb_set_page_with_attrs:
|
||||
* @cpu: CPU to add this TLB entry for
|
||||
* @addr: virtual address of page to add entry for
|
||||
* @paddr: physical address of the page
|
||||
* @attrs: memory transaction attributes
|
||||
* @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
|
||||
* @mmu_idx: MMU index to insert TLB entry for
|
||||
* @size: size of the page in bytes
|
||||
*
|
||||
* Add an entry to this CPU's TLB (a mapping from virtual address
|
||||
* @addr to physical address @paddr) with the specified memory
|
||||
* transaction attributes. This is generally called by the target CPU
|
||||
* specific code after it has been called through the tlb_fill()
|
||||
* entry point and performed a successful page table walk to find
|
||||
* the physical address and attributes for the virtual address
|
||||
* which provoked the TLB miss.
|
||||
*
|
||||
* At most one entry for a given virtual address is permitted. Only a
|
||||
* single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
|
||||
* used by tlb_flush_page.
|
||||
*/
|
||||
void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
|
||||
hwaddr paddr, MemTxAttrs attrs,
|
||||
int prot, int mmu_idx, vaddr size);
|
||||
/* tlb_set_page:
|
||||
*
|
||||
* This function is equivalent to calling tlb_set_page_with_attrs()
|
||||
* with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
|
||||
* as a convenience for CPUs which don't use memory transaction attributes.
|
||||
*/
|
||||
void tlb_set_page(CPUState *cpu, vaddr addr,
|
||||
hwaddr paddr, int prot,
|
||||
int mmu_idx, vaddr size);
|
||||
#else
|
||||
static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush(CPUState *cpu)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
|
||||
vaddr addr, uint16_t idxmap)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
||||
vaddr addr,
|
||||
uint16_t idxmap)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
||||
uint16_t idxmap)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
|
||||
vaddr addr,
|
||||
uint16_t idxmap,
|
||||
unsigned bits)
|
||||
{
|
||||
}
|
||||
static inline void
|
||||
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
|
||||
uint16_t idxmap, unsigned bits)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
|
||||
vaddr len, uint16_t idxmap,
|
||||
unsigned bits)
|
||||
{
|
||||
}
|
||||
static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
||||
vaddr addr,
|
||||
vaddr len,
|
||||
uint16_t idxmap,
|
||||
unsigned bits)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TCG)
|
||||
#include "accel/tcg/getpc.h"
|
||||
|
||||
/**
|
||||
* probe_access:
|
||||
|
|
@ -417,24 +178,6 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
|
|||
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last);
|
||||
void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
|
||||
|
||||
/* GETPC is the true target of the return instruction that we'll execute. */
|
||||
#if defined(CONFIG_TCG_INTERPRETER)
|
||||
extern __thread uintptr_t tci_tb_ptr;
|
||||
# define GETPC() tci_tb_ptr
|
||||
#else
|
||||
# define GETPC() \
|
||||
((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
|
||||
#endif
|
||||
|
||||
/* The true return address will often point to a host insn that is part of
|
||||
the next translated guest insn. Adjust the address backward to point to
|
||||
the middle of the call insn. Subtracting one would do the job except for
|
||||
several compressed mode architectures (arm, mips) which set the low bit
|
||||
to indicate the compressed mode; subtracting two works around that. It
|
||||
is also the case that there are no host isas that contain a call insn
|
||||
smaller than 4 bytes, so we don't worry about special-casing this. */
|
||||
#define GETPC_ADJ 2
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
/**
|
||||
|
|
@ -486,9 +229,6 @@ static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
|
|||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
|
||||
void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
|
||||
|
||||
MemoryRegionSection *
|
||||
address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
|
||||
hwaddr *xlat, hwaddr *plen,
|
||||
|
|
|
|||
|
|
@ -44,25 +44,8 @@
|
|||
#pragma GCC poison TARGET_FMT_ld
|
||||
#pragma GCC poison TARGET_FMT_lu
|
||||
|
||||
#pragma GCC poison TARGET_PAGE_SIZE
|
||||
#pragma GCC poison TARGET_PAGE_MASK
|
||||
#pragma GCC poison TARGET_PAGE_BITS
|
||||
#pragma GCC poison TARGET_PAGE_ALIGN
|
||||
#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS
|
||||
|
||||
#pragma GCC poison CPU_INTERRUPT_HARD
|
||||
#pragma GCC poison CPU_INTERRUPT_EXITTB
|
||||
#pragma GCC poison CPU_INTERRUPT_HALT
|
||||
#pragma GCC poison CPU_INTERRUPT_DEBUG
|
||||
#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
|
||||
#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
|
||||
#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2
|
||||
#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3
|
||||
#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4
|
||||
#pragma GCC poison CPU_INTERRUPT_TGT_INT_0
|
||||
#pragma GCC poison CPU_INTERRUPT_TGT_INT_1
|
||||
#pragma GCC poison CPU_INTERRUPT_TGT_INT_2
|
||||
|
||||
#pragma GCC poison CONFIG_ALPHA_DIS
|
||||
#pragma GCC poison CONFIG_HPPA_DIS
|
||||
#pragma GCC poison CONFIG_I386_DIS
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include "cpu.h"
|
||||
#include "system/xen.h"
|
||||
#include "system/tcg.h"
|
||||
#include "exec/cputlb.h"
|
||||
#include "exec/ramlist.h"
|
||||
#include "exec/ramblock.h"
|
||||
#include "exec/exec-all.h"
|
||||
|
|
|
|||
|
|
@ -14,10 +14,56 @@
|
|||
#ifndef EXEC_TARGET_PAGE_H
|
||||
#define EXEC_TARGET_PAGE_H
|
||||
|
||||
size_t qemu_target_page_size(void);
|
||||
int qemu_target_page_mask(void);
|
||||
int qemu_target_page_bits(void);
|
||||
int qemu_target_page_bits_min(void);
|
||||
|
||||
size_t qemu_target_pages_to_MiB(size_t pages);
|
||||
/*
|
||||
* If compiling per-target, get the real values.
|
||||
* For generic code, reuse the mechanism for variable page size.
|
||||
*/
|
||||
#ifdef COMPILING_PER_TARGET
|
||||
#include "cpu-param.h"
|
||||
#include "exec/target_long.h"
|
||||
#define TARGET_PAGE_TYPE target_long
|
||||
#else
|
||||
#define TARGET_PAGE_BITS_VARY
|
||||
#define TARGET_PAGE_TYPE int
|
||||
#endif
|
||||
|
||||
#ifdef TARGET_PAGE_BITS_VARY
|
||||
# include "exec/page-vary.h"
|
||||
extern const TargetPageBits target_page;
|
||||
# ifdef CONFIG_DEBUG_TCG
|
||||
# define TARGET_PAGE_BITS ({ assert(target_page.decided); \
|
||||
target_page.bits; })
|
||||
# define TARGET_PAGE_MASK ({ assert(target_page.decided); \
|
||||
(TARGET_PAGE_TYPE)target_page.mask; })
|
||||
# else
|
||||
# define TARGET_PAGE_BITS target_page.bits
|
||||
# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)target_page.mask)
|
||||
# endif
|
||||
# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
|
||||
#else
|
||||
# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
|
||||
# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
|
||||
# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)-1 << TARGET_PAGE_BITS)
|
||||
#endif
|
||||
|
||||
#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
|
||||
|
||||
static inline size_t qemu_target_page_size(void)
|
||||
{
|
||||
return TARGET_PAGE_SIZE;
|
||||
}
|
||||
|
||||
static inline int qemu_target_page_mask(void)
|
||||
{
|
||||
return TARGET_PAGE_MASK;
|
||||
}
|
||||
|
||||
static inline int qemu_target_page_bits(void)
|
||||
{
|
||||
return TARGET_PAGE_BITS;
|
||||
}
|
||||
|
||||
int qemu_target_page_bits_min(void);
|
||||
size_t qemu_target_pages_to_MiB(size_t pages);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue