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Zeroing ITR shouldn't ack irq zero.

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Fix PWT & PWL clocks, fix user refcounting for clocks, add 'hsab_ck' and 'usb_w2fc_ck'.
Fix TCMI register addresses.
Implement OMAP McBSP controller and connection to I2S-compatible CODECs.
Add audio support for TSC2102 as an I2S CODEC.
Connect TSC2102 I2S interface to CPU's McBSP1 interface in the Palm Tungsten|E.
Correct '>' instead of '>>' typos.
Implement GPIO PIN_CONTROL register (not in OMAP310 TRM, from OMAP1510).


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3534 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2007-11-04 22:53:50 +00:00
parent bfa30a3896
commit d8f699cb32
6 changed files with 858 additions and 61 deletions
Download patch file Download diff file Expand all files Collapse all files

123
hw/omap.h
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@ -479,6 +479,30 @@ struct omap_rtc_s;
struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
qemu_irq *irq, omap_clk clk);
struct i2s_codec_s {
void *opaque;
/* The CPU can call this if it is generating the clock signal on the
* i2s port. The CODEC can ignore it if it is set up as a clock
* master and generates its own clock. */
void (*set_rate)(void *opaque, int in, int out);
void (*tx_swallow)(void *opaque);
qemu_irq rx_swallow;
qemu_irq tx_start;
struct i2s_fifo_s {
uint8_t *fifo;
int len;
int start;
int size;
} in, out;
};
struct omap_mcbsp_s;
struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
qemu_irq *irq, qemu_irq *dma, omap_clk clk);
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
/* omap_lcdc.c */
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
@ -536,6 +560,9 @@ struct omap_mpu_state_s {
struct omap_gpio_s *gpio;
struct omap_mcbsp_s *mcbsp1;
struct omap_mcbsp_s *mcbsp3;
/* MPU public TIPB peripherals */
struct omap_32khz_timer_s *os_timer;
@ -563,6 +590,8 @@ struct omap_mpu_state_s {
struct omap_rtc_s *rtc;
struct omap_mcbsp_s *mcbsp2;
/* MPU private TIPB peripherals */
struct omap_intr_handler_s *ih[2];
@ -646,6 +675,7 @@ void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
__FUNCTION__, paddr)
# define TCMI_VERBOSE 1
//# define MEM_VERBOSE 1
# ifdef TCMI_VERBOSE
# define OMAP_8B_REG(paddr) \
@ -665,4 +695,97 @@ void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
# define OMAP_MPUI_REG_MASK 0x000007ff
# ifdef MEM_VERBOSE
struct io_fn {
CPUReadMemoryFunc **mem_read;
CPUWriteMemoryFunc **mem_write;
void *opaque;
int in;
};
static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
{
struct io_fn *s = opaque;
uint32_t ret;
s->in ++;
ret = s->mem_read[0](s->opaque, addr);
s->in --;
if (!s->in)
fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
return ret;
}
static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
{
struct io_fn *s = opaque;
uint32_t ret;
s->in ++;
ret = s->mem_read[1](s->opaque, addr);
s->in --;
if (!s->in)
fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
return ret;
}
static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
{
struct io_fn *s = opaque;
uint32_t ret;
s->in ++;
ret = s->mem_read[2](s->opaque, addr);
s->in --;
if (!s->in)
fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
return ret;
}
static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct io_fn *s = opaque;
if (!s->in)
fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
s->in ++;
s->mem_write[0](s->opaque, addr, value);
s->in --;
}
static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct io_fn *s = opaque;
if (!s->in)
fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
s->in ++;
s->mem_write[1](s->opaque, addr, value);
s->in --;
}
static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct io_fn *s = opaque;
if (!s->in)
fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
s->in ++;
s->mem_write[2](s->opaque, addr, value);
s->in --;
}
static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
inline static int debug_register_io_memory(int io_index,
CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
void *opaque)
{
struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
s->mem_read = mem_read;
s->mem_write = mem_write;
s->opaque = opaque;
s->in = 0;
return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
}
# define cpu_register_io_memory debug_register_io_memory
# endif
#endif /* hw_omap_h */