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target/riscv: rvk: add support for zbkb extension

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- reuse partial instructions of zbb extension, update extension check for them
 - add brev8, pack, packh, packw, unzip, zip instructions

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2022-04-23 10:34:58 +08:00 • committed by Alistair Francis
parent eef82872be
commit d8e81e3c18
5 changed files with 174 additions and 28 deletions
Download patch file Download diff file Expand all files Collapse all files

94
target/riscv/insn_trans/trans_rvb.c.inc
View file

@ -1,5 +1,5 @@
/*
* RISC-V translation routines for the Zb[abcs] Standard Extension.
* RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@ -42,6 +42,12 @@
} \
} while (0)
#define REQUIRE_ZBKB(ctx) do { \
if (!ctx->cfg_ptr->ext_zbkb) { \
return false; \
} \
} while (0)
static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
@ -85,19 +91,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
REQUIRE_ZBB(ctx);
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
REQUIRE_ZBB(ctx);
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
REQUIRE_ZBB(ctx);
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_eqv_tl);
}
@ -247,7 +253,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
REQUIRE_ZBB(ctx);
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
}
@ -264,7 +270,7 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
static bool trans_rori(DisasContext *ctx, arg_rori *a)
{
REQUIRE_ZBB(ctx);
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
tcg_gen_rotri_tl, gen_roriw, NULL);
}
@ -289,7 +295,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_rol(DisasContext *ctx, arg_rol *a)
{
REQUIRE_ZBB(ctx);
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
}
@ -301,14 +307,14 @@ static void gen_rev8_32(TCGv ret, TCGv src1)
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_32BIT(ctx);
REQUIRE_ZBB(ctx);
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
}
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
}
@ -403,7 +409,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
}
@ -411,7 +417,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
}
@ -419,7 +425,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
}
@ -504,3 +510,67 @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
REQUIRE_ZBC(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
}
static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
{
tcg_gen_deposit_tl(ret, src1, src2,
TARGET_LONG_BITS / 2,
TARGET_LONG_BITS / 2);
}
static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
{
TCGv t = tcg_temp_new();
tcg_gen_ext8u_tl(t, src2);
tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
tcg_temp_free(t);
}
static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
{
TCGv t = tcg_temp_new();
tcg_gen_ext16s_tl(t, src2);
tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16);
tcg_temp_free(t);
}
static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
{
REQUIRE_ZBKB(ctx);
return gen_unary(ctx, a, EXT_NONE, gen_helper_brev8);
}
static bool trans_pack(DisasContext *ctx, arg_pack *a)
{
REQUIRE_ZBKB(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
}
static bool trans_packh(DisasContext *ctx, arg_packh *a)
{
REQUIRE_ZBKB(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
}
static bool trans_packw(DisasContext *ctx, arg_packw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBKB(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
}
static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
{
REQUIRE_32BIT(ctx);
REQUIRE_ZBKB(ctx);
return gen_unary(ctx, a, EXT_NONE, gen_helper_unzip);
}
static bool trans_zip(DisasContext *ctx, arg_zip *a)
{
REQUIRE_32BIT(ctx);
REQUIRE_ZBKB(ctx);
return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
}