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target/sparc: Split fcc out of env->fsr
Represent each fcc field separately from the rest of fsr. This vastly simplifies floating-point comparisons. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-22-richard.henderson@linaro.org>
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4 changed files with 201 additions and 525 deletions
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@ -31,8 +31,10 @@
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#if !defined(TARGET_SPARC64)
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#define TARGET_DPREGS 16
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#define TARGET_FCCREGS 1
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#else
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#define TARGET_DPREGS 32
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#define TARGET_FCCREGS 4
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#endif
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/*#define EXCP_INTERRUPT 0x100*/
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@ -203,24 +205,19 @@ enum {
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#ifdef TARGET_SPARC64
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#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
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#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
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#define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
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#define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
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#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
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#else
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#define FSR_FTT_NMASK 0xfffe3fffULL
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#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
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#define FSR_LDFSR_OLDMASK 0x000fc000ULL
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#endif
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#define FSR_LDFSR_MASK 0xcfc00fffULL
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#define FSR_FTT_IEEE_EXCP (1ULL << 14)
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#define FSR_FTT_UNIMPFPOP (3ULL << 14)
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#define FSR_FTT_SEQ_ERROR (4ULL << 14)
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#define FSR_FTT_INVAL_FPR (6ULL << 14)
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#define FSR_FCC1_SHIFT 11
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#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
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#define FSR_FCC0_SHIFT 10
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#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
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#define FSR_FCC0_SHIFT 10
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#define FSR_FCC1_SHIFT 32
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#define FSR_FCC2_SHIFT 34
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#define FSR_FCC3_SHIFT 36
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/* MMU */
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#define MMU_E (1<<0)
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@ -467,8 +464,9 @@ struct CPUArchState {
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temporary register when possible) */
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/* FPU State Register, in parts */
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target_ulong fsr; /* rm, tem, aexc, fcc* */
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uint32_t fsr_cexc_ftt; /* cexc, ftt */
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uint32_t fsr; /* rm, tem, aexc */
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uint32_t fsr_cexc_ftt; /* cexc, ftt */
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uint32_t fcc[TARGET_FCCREGS]; /* fcc* */
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CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */
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uint32_t cwp; /* index of current register window (extracted
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