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target/openrisc: implement shadow registers

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Shadow registers are part of the openrisc spec along with sr[cid], as
part of the fast context switching feature.  When exceptions occur,
instead of having to save registers to the stack if enabled the CID will
increment and a new set of registers will be available.

This patch only implements shadow registers which can be used as extra
scratch registers via the mfspr and mtspr if required.  This is
implemented in a way where it would be easy to add on the fast context
switching, currently cid is hardcoded to 0.

This is need for openrisc linux smp kernels to boot correctly.

Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Stafford Horne 2017-04-06 06:44:56 +09:00
parent 4597992f62
commit d89e71e873
11 changed files with 56 additions and 32 deletions
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15
target/openrisc/cpu.h
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@ -275,7 +275,8 @@ typedef struct CPUOpenRISCTLBContext {
#endif
typedef struct CPUOpenRISCState {
target_ulong gpr[32]; /* General registers */
target_ulong shadow_gpr[16][32]; /* Shadow registers */
target_ulong pc; /* Program counter */
target_ulong ppc; /* Prev PC */
target_ulong jmp_pc; /* Jump PC */
@ -399,6 +400,16 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
#define TB_FLAGS_R0_0 2
#define TB_FLAGS_OVE SR_OVE
static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i)
{
return env->shadow_gpr[0][i];
}
static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val)
{
env->shadow_gpr[0][i] = val;
}
static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
@ -406,7 +417,7 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
*pc = env->pc;
*cs_base = 0;
*flags = (env->dflag
| (env->gpr[0] == 0 ? TB_FLAGS_R0_0 : 0)
| (cpu_get_gpr(env, 0) == 0 ? TB_FLAGS_R0_0 : 0)
| (env->sr & SR_OVE));
}