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target/openrisc: implement shadow registers

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Shadow registers are part of the openrisc spec along with sr[cid], as
part of the fast context switching feature.  When exceptions occur,
instead of having to save registers to the stack if enabled the CID will
increment and a new set of registers will be available.

This patch only implements shadow registers which can be used as extra
scratch registers via the mfspr and mtspr if required.  This is
implemented in a way where it would be easy to add on the fast context
switching, currently cid is hardcoded to 0.

This is need for openrisc linux smp kernels to boot correctly.

Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Stafford Horne 2017-04-06 06:44:56 +09:00
parent 4597992f62
commit d89e71e873
11 changed files with 56 additions and 32 deletions
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6
linux-user/openrisc/target_cpu.h
View file

@ -23,14 +23,14 @@
static inline void cpu_clone_regs(CPUOpenRISCState *env, target_ulong newsp)
{
if (newsp) {
env->gpr[1] = newsp;
cpu_set_gpr(env, 1, newsp);
}
env->gpr[11] = 0;
cpu_set_gpr(env, 11, 0);
}
static inline void cpu_set_tls(CPUOpenRISCState *env, target_ulong newtls)
{
env->gpr[10] = newtls;
cpu_set_gpr(env, 10, newtls);
}
#endif