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target/openrisc: implement shadow registers

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Shadow registers are part of the openrisc spec along with sr[cid], as
part of the fast context switching feature.  When exceptions occur,
instead of having to save registers to the stack if enabled the CID will
increment and a new set of registers will be available.

This patch only implements shadow registers which can be used as extra
scratch registers via the mfspr and mtspr if required.  This is
implemented in a way where it would be easy to add on the fast context
switching, currently cid is hardcoded to 0.

This is need for openrisc linux smp kernels to boot correctly.

Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Stafford Horne 2017-04-06 06:44:56 +09:00
parent 4597992f62
commit d89e71e873
11 changed files with 56 additions and 32 deletions
Download patch file Download diff file Expand all files Collapse all files

2
linux-user/elfload.c
View file

@ -1052,7 +1052,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
int i;
for (i = 0; i < 32; i++) {
(*regs)[i] = tswapreg(env->gpr[i]);
(*regs)[i] = tswapreg(cpu_get_gpr(env, i));
}
(*regs)[32] = tswapreg(env->pc);
(*regs)[33] = tswapreg(cpu_get_sr(env));

18
linux-user/main.c
View file

@ -2590,17 +2590,17 @@ void cpu_loop(CPUOpenRISCState *env)
case EXCP_SYSCALL:
env->pc += 4; /* 0xc00; */
ret = do_syscall(env,
env->gpr[11], /* return value */
env->gpr[3], /* r3 - r7 are params */
env->gpr[4],
env->gpr[5],
env->gpr[6],
env->gpr[7],
env->gpr[8], 0, 0);
cpu_get_gpr(env, 11), /* return value */
cpu_get_gpr(env, 3), /* r3 - r7 are params */
cpu_get_gpr(env, 4),
cpu_get_gpr(env, 5),
cpu_get_gpr(env, 6),
cpu_get_gpr(env, 7),
cpu_get_gpr(env, 8), 0, 0);
if (ret == -TARGET_ERESTARTSYS) {
env->pc -= 4;
} else if (ret != -TARGET_QEMU_ESIGRETURN) {
env->gpr[11] = ret;
cpu_set_gpr(env, 11, ret);
}
break;
case EXCP_DPF:
@ -4765,7 +4765,7 @@ int main(int argc, char **argv, char **envp)
int i;
for (i = 0; i < 32; i++) {
env->gpr[i] = regs->gpr[i];
cpu_set_gpr(env, i, regs->gpr[i]);
}
env->pc = regs->pc;
cpu_set_sr(env, regs->sr);

6
linux-user/openrisc/target_cpu.h
View file

@ -23,14 +23,14 @@
static inline void cpu_clone_regs(CPUOpenRISCState *env, target_ulong newsp)
{
if (newsp) {
env->gpr[1] = newsp;
cpu_set_gpr(env, 1, newsp);
}
env->gpr[11] = 0;
cpu_set_gpr(env, 11, 0);
}
static inline void cpu_set_tls(CPUOpenRISCState *env, target_ulong newtls)
{
env->gpr[10] = newtls;
cpu_set_gpr(env, 10, newtls);
}
#endif

2
linux-user/openrisc/target_signal.h
View file

@ -20,7 +20,7 @@ typedef struct target_sigaltstack {
static inline abi_ulong get_sp_from_cpustate(CPUOpenRISCState *state)
{
return state->gpr[1];
return cpu_get_gpr(state, 1);
}

17
linux-user/signal.c
View file

@ -4411,7 +4411,7 @@ static void setup_sigcontext(struct target_sigcontext *sc,
CPUOpenRISCState *regs,
unsigned long mask)
{
unsigned long usp = regs->gpr[1];
unsigned long usp = cpu_get_gpr(regs, 1);
/* copy the regs. they are first in sc so we can use sc directly */
@ -4436,7 +4436,7 @@ static inline abi_ulong get_sigframe(struct target_sigaction *ka,
CPUOpenRISCState *regs,
size_t frame_size)
{
unsigned long sp = regs->gpr[1];
unsigned long sp = cpu_get_gpr(regs, 1);
int onsigstack = on_sig_stack(sp);
/* redzone */
@ -4489,7 +4489,8 @@ static void setup_rt_frame(int sig, struct target_sigaction *ka,
__put_user(0, &frame->uc.tuc_link);
__put_user(target_sigaltstack_used.ss_sp,
&frame->uc.tuc_stack.ss_sp);
__put_user(sas_ss_flags(env->gpr[1]), &frame->uc.tuc_stack.ss_flags);
__put_user(sas_ss_flags(cpu_get_gpr(env, 1)),
&frame->uc.tuc_stack.ss_flags);
__put_user(target_sigaltstack_used.ss_size,
&frame->uc.tuc_stack.ss_size);
setup_sigcontext(&frame->sc, env, set->sig[0]);
@ -4512,13 +4513,13 @@ static void setup_rt_frame(int sig, struct target_sigaction *ka,
/* Set up registers for signal handler */
env->pc = (unsigned long)ka->_sa_handler; /* what we enter NOW */
env->gpr[9] = (unsigned long)return_ip; /* what we enter LATER */
env->gpr[3] = (unsigned long)sig; /* arg 1: signo */
env->gpr[4] = (unsigned long)&frame->info; /* arg 2: (siginfo_t*) */
env->gpr[5] = (unsigned long)&frame->uc; /* arg 3: ucontext */
cpu_set_gpr(env, 9, (unsigned long)return_ip); /* what we enter LATER */
cpu_set_gpr(env, 3, (unsigned long)sig); /* arg 1: signo */
cpu_set_gpr(env, 4, (unsigned long)&frame->info); /* arg 2: (siginfo_t*) */
cpu_set_gpr(env, 5, (unsigned long)&frame->uc); /* arg 3: ucontext */
/* actually move the usp to reflect the stacked frame */
env->gpr[1] = (unsigned long)frame;
cpu_set_gpr(env, 1, (unsigned long)frame);
return;