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Add CPUClass::tlb_fill.
Improve tlb_vaddr_to_host for use by ARM SVE no-fault loads. -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAlzVx4UdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+U1Af/b3cV5d5a1LWRdLgR 71JCPK/M3o43r2U9wCSikteXkmNBEdEoc5+WRk2SuZFLW/JB1DHDY7/gISPIhfoB ZIza2TxD/QK1CQ5/mMWruKBlyygbYYZgsYaaNsMJRJgicgOSjTN0nuHMbIfv3tAN mu+IlkD0LdhVjP0fz30Jpew3b3575RCjYxEPM6KQI3RxtQFjZ3FhqV5hKR4vtdP5 yLWJQzwAbaCB3SZUvvp7TN1ZsmeyLpc+Yz/YtRTqQedo7SNWWBKldLhqq4bZnH1I AkzHbtWIOBrjWJ34ZMAgI5Q56Du9TBbBvCdM9azmrQjSu/2kdsPBPcUyOpnUCsCx NyXo9g== =x71l -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into staging Add CPUClass::tlb_fill. Improve tlb_vaddr_to_host for use by ARM SVE no-fault loads. # gpg: Signature made Fri 10 May 2019 19:48:37 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190510: (27 commits) tcg: Use tlb_fill probe from tlb_vaddr_to_host tcg: Remove CPUClass::handle_mmu_fault tcg: Use CPUClass::tlb_fill in cputlb.c target/xtensa: Convert to CPUClass::tlb_fill target/unicore32: Convert to CPUClass::tlb_fill target/tricore: Convert to CPUClass::tlb_fill target/tilegx: Convert to CPUClass::tlb_fill target/sparc: Convert to CPUClass::tlb_fill target/sh4: Convert to CPUClass::tlb_fill target/s390x: Convert to CPUClass::tlb_fill target/riscv: Convert to CPUClass::tlb_fill target/ppc: Convert to CPUClass::tlb_fill target/openrisc: Convert to CPUClass::tlb_fill target/nios2: Convert to CPUClass::tlb_fill target/moxie: Convert to CPUClass::tlb_fill target/mips: Convert to CPUClass::tlb_fill target/mips: Tidy control flow in mips_cpu_handle_mmu_fault target/mips: Pass a valid error to raise_mmu_exception for user-only target/microblaze: Convert to CPUClass::tlb_fill target/m68k: Convert to CPUClass::tlb_fill ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
d8276573da
83 changed files with 868 additions and 1131 deletions
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@ -433,50 +433,20 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
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* @mmu_idx: MMU index to use for lookup
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*
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* Look up the specified guest virtual index in the TCG softmmu TLB.
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* If the TLB contains a host virtual address suitable for direct RAM
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* access, then return it. Otherwise (TLB miss, TLB entry is for an
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* I/O access, etc) return NULL.
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*
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* This is the equivalent of the initial fast-path code used by
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* TCG backends for guest load and store accesses.
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* If we can translate a host virtual address suitable for direct RAM
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* access, without causing a guest exception, then return it.
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* Otherwise (TLB entry is for an I/O access, guest software
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* TLB fill required, etc) return NULL.
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*/
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#ifdef CONFIG_USER_ONLY
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static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
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int access_type, int mmu_idx)
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MMUAccessType access_type, int mmu_idx)
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{
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#if defined(CONFIG_USER_ONLY)
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return g2h(addr);
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#else
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CPUTLBEntry *tlbentry = tlb_entry(env, mmu_idx, addr);
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abi_ptr tlb_addr;
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uintptr_t haddr;
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switch (access_type) {
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case 0:
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tlb_addr = tlbentry->addr_read;
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break;
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case 1:
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tlb_addr = tlb_addr_write(tlbentry);
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break;
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case 2:
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tlb_addr = tlbentry->addr_code;
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break;
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default:
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g_assert_not_reached();
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}
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if (!tlb_hit(tlb_addr, addr)) {
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/* TLB entry is for a different page */
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return NULL;
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}
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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return NULL;
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}
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haddr = addr + tlbentry->addend;
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return (void *)haddr;
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#endif /* defined(CONFIG_USER_ONLY) */
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}
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#else
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void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
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MMUAccessType access_type, int mmu_idx);
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#endif
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#endif /* CPU_LDST_H */
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@ -474,15 +474,6 @@ static inline void assert_no_pages_locked(void)
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*/
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struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
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hwaddr index, MemTxAttrs attrs);
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/*
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* Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
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* caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
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* be discarded and looked up again (e.g. via tlb_entry()).
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*/
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void tlb_fill(CPUState *cpu, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
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#endif
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#if defined(CONFIG_USER_ONLY)
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