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target-arm queue:

Browse source 
* linux-user/elfload: Add missing arm64 hwcap values
  * stellaris-gamepad: Convert to qdev
  * docs/specs: Convert various txt docs to rST
  * MAINTAINERS: Make sure that gicv3_internal.h is covered, too
  * hw/arm/pxa2xx_gpio: Pass CPU using QOM link property
  * hw/watchdog/wdt_imx2: Trace MMIO access and timer activity
  * hw/misc/imx7_snvs: Trace MMIO access
  * hw/misc/imx6_ccm: Convert DPRINTF to trace events
  * hw/i2c/pm_smbus: Convert DPRINTF to trace events
  * target/arm: Enable FEAT_MOPS insns in user-mode emulation
  * linux-user: Report AArch64 hwcap2 fields above bit 31
  * target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly
  * target/arm: Fix SVE STR increment
  * hw/char/stm32f2xx_usart: implement TX interrupts
  * target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk
  * xlnx-versal-virt: Add AMD/Xilinx TRNG device
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Merge tag 'pull-target-arm-20231102' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * linux-user/elfload: Add missing arm64 hwcap values
 * stellaris-gamepad: Convert to qdev
 * docs/specs: Convert various txt docs to rST
 * MAINTAINERS: Make sure that gicv3_internal.h is covered, too
 * hw/arm/pxa2xx_gpio: Pass CPU using QOM link property
 * hw/watchdog/wdt_imx2: Trace MMIO access and timer activity
 * hw/misc/imx7_snvs: Trace MMIO access
 * hw/misc/imx6_ccm: Convert DPRINTF to trace events
 * hw/i2c/pm_smbus: Convert DPRINTF to trace events
 * target/arm: Enable FEAT_MOPS insns in user-mode emulation
 * linux-user: Report AArch64 hwcap2 fields above bit 31
 * target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly
 * target/arm: Fix SVE STR increment
 * hw/char/stm32f2xx_usart: implement TX interrupts
 * target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk
 * xlnx-versal-virt: Add AMD/Xilinx TRNG device

* tag 'pull-target-arm-20231102' of https://git.linaro.org/people/pmaydell/qemu-arm: (33 commits)
  tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG device
  hw/arm: xlnx-versal-virt: Add AMD/Xilinx TRNG device
  hw/misc: Introduce AMD/Xilix Versal TRNG device
  target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk
  hw/char/stm32f2xx_usart: Add more definitions for CR1 register
  hw/char/stm32f2xx_usart: Update IRQ when DR is written
  hw/char/stm32f2xx_usart: Extract common IRQ update code to update_irq()
  target/arm: Fix SVE STR increment
  target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly
  linux-user: Report AArch64 hwcap2 fields above bit 31
  target/arm: Enable FEAT_MOPS insns in user-mode emulation
  hw/i2c/pm_smbus: Convert DPRINTF to trace events
  hw/misc/imx6_ccm: Convert DPRINTF to trace events
  hw/misc/imx7_snvs: Trace MMIO access
  hw/watchdog/wdt_imx2: Trace timer activity
  hw/watchdog/wdt_imx2: Trace MMIO access
  hw/arm/pxa2xx_gpio: Pass CPU using QOM link property
  MAINTAINERS: Make sure that gicv3_internal.h is covered, too
  docs/specs/vmgenid: Convert to rST
  docs/specs/vmcoreinfo: Convert to rST
  ...

Conflicts:
  hw/input/stellaris_input.c
  The qdev conversion in this pull request ("stellaris-gamepad: Convert
  to qdev") eliminates the vmstate_register() call that was converted to
  vmstate_register_any() in the conflicting migration pull request.
  vmstate_register_any() is no longer necessary now that this device has
  been converted to qdev, so take this pull request's version of
  stellaris_gamepad.c over the previous pull request's
  stellaris_input.c (the file was renamed).

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-11-03 10:04:12 +08:00
commit d762bf9793
56 changed files with 2302 additions and 776 deletions
Download patch file Download diff file Expand all files Collapse all files

3
hw/arm/Kconfig
View file

@ -291,7 +291,7 @@ config STELLARIS
select SSD0303 # OLED display
select SSD0323 # OLED display
select SSI_SD
select STELLARIS_INPUT
select STELLARIS_GAMEPAD
select STELLARIS_ENET # ethernet
select STELLARIS_GPTM # general purpose timer module
select UNIMP
@ -482,6 +482,7 @@ config XLNX_VERSAL
select XLNX_BBRAM
select XLNX_EFUSE_VERSAL
select XLNX_USB_SUBSYS
select XLNX_VERSAL_TRNG
config NPCM7XX
bool

8
hw/arm/pxa2xx_gpio.c
View file

@ -32,7 +32,6 @@ struct PXA2xxGPIOInfo {
MemoryRegion iomem;
qemu_irq irq0, irq1, irqX;
int lines;
int ncpu;
ARMCPU *cpu;
/* XXX: GNU C vectors are more suitable */
@ -266,12 +265,11 @@ static const MemoryRegionOps pxa_gpio_ops = {
DeviceState *pxa2xx_gpio_init(hwaddr base,
ARMCPU *cpu, DeviceState *pic, int lines)
{
CPUState *cs = CPU(cpu);
DeviceState *dev;
dev = qdev_new(TYPE_PXA2XX_GPIO);
qdev_prop_set_int32(dev, "lines", lines);
qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
@ -303,8 +301,6 @@ static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
{
PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
qdev_init_gpio_out(dev, s->handler, s->lines);
}
@ -339,7 +335,7 @@ static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
static Property pxa2xx_gpio_properties[] = {
DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
DEFINE_PROP_LINK("cpu", PXA2xxGPIOInfo, cpu, TYPE_ARM_CPU, ARMCPU *),
DEFINE_PROP_END_OF_LIST(),
};

34
hw/arm/stellaris.c
View file

@ -23,7 +23,7 @@
#include "sysemu/sysemu.h"
#include "hw/arm/armv7m.h"
#include "hw/char/pl011.h"
#include "hw/input/gamepad.h"
#include "hw/input/stellaris_gamepad.h"
#include "hw/irq.h"
#include "hw/watchdog/cmsdk-apb-watchdog.h"
#include "migration/vmstate.h"
@ -31,6 +31,8 @@
#include "hw/timer/stellaris-gptm.h"
#include "hw/qdev-clock.h"
#include "qom/object.h"
#include "qapi/qmp/qlist.h"
#include "ui/input.h"
#define GPIO_A 0
#define GPIO_B 1
@ -1274,16 +1276,30 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
}
if (board->peripherals & BP_GAMEPAD) {
qemu_irq gpad_irq[5];
static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
QList *gpad_keycode_list = qlist_new();
static const int gpad_keycode[5] = {
Q_KEY_CODE_UP, Q_KEY_CODE_DOWN, Q_KEY_CODE_LEFT,
Q_KEY_CODE_RIGHT, Q_KEY_CODE_CTRL,
};
DeviceState *gpad;
gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
}
qdev_prop_set_array(gpad, "keycodes", gpad_keycode_list);
sysbus_realize_and_unref(SYS_BUS_DEVICE(gpad), &error_fatal);
stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
qdev_connect_gpio_out(gpad, 0,
qemu_irq_invert(gpio_in[GPIO_E][0])); /* up */
qdev_connect_gpio_out(gpad, 1,
qemu_irq_invert(gpio_in[GPIO_E][1])); /* down */
qdev_connect_gpio_out(gpad, 2,
qemu_irq_invert(gpio_in[GPIO_E][2])); /* left */
qdev_connect_gpio_out(gpad, 3,
qemu_irq_invert(gpio_in[GPIO_E][3])); /* right */
qdev_connect_gpio_out(gpad, 4,
qemu_irq_invert(gpio_in[GPIO_F][1])); /* select */
}
for (i = 0; i < 7; i++) {
if (board->dc4 & (1 << i)) {

16
hw/arm/xlnx-versal.c
View file

@ -373,6 +373,21 @@ static void versal_create_rtc(Versal *s, qemu_irq *pic)
qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0));
}
static void versal_create_trng(Versal *s, qemu_irq *pic)
{
SysBusDevice *sbd;
MemoryRegion *mr;
object_initialize_child(OBJECT(s), "trng", &s->pmc.trng,
TYPE_XLNX_VERSAL_TRNG);
sbd = SYS_BUS_DEVICE(&s->pmc.trng);
sysbus_realize(sbd, &error_fatal);
mr = sysbus_mmio_get_region(sbd, 0);
memory_region_add_subregion(&s->mr_ps, MM_PMC_TRNG, mr);
sysbus_connect_irq(sbd, 0, pic[VERSAL_TRNG_IRQ]);
}
static void versal_create_xrams(Versal *s, qemu_irq *pic)
{
int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl);
@ -909,6 +924,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_sds(s, pic);
versal_create_pmc_apb_irq_orgate(s, pic);
versal_create_rtc(s, pic);
versal_create_trng(s, pic);
versal_create_xrams(s, pic);
versal_create_bbram(s, pic);
versal_create_efuse(s, pic);

29
hw/char/stm32f2xx_usart.c
View file

@ -53,6 +53,17 @@ static int stm32f2xx_usart_can_receive(void *opaque)
return 0;
}
static void stm32f2xx_update_irq(STM32F2XXUsartState *s)
{
uint32_t mask = s->usart_sr & s->usart_cr1;
if (mask & (USART_SR_TXE | USART_SR_TC | USART_SR_RXNE)) {
qemu_set_irq(s->irq, 1);
} else {
qemu_set_irq(s->irq, 0);
}
}
static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
{
STM32F2XXUsartState *s = opaque;
@ -66,9 +77,7 @@ static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
s->usart_dr = *buf;
s->usart_sr |= USART_SR_RXNE;
if (s->usart_cr1 & USART_CR1_RXNEIE) {
qemu_set_irq(s->irq, 1);
}
stm32f2xx_update_irq(s);
DB_PRINT("Receiving: %c\n", s->usart_dr);
}
@ -85,7 +94,7 @@ static void stm32f2xx_usart_reset(DeviceState *dev)
s->usart_cr3 = 0x00000000;
s->usart_gtpr = 0x00000000;
qemu_set_irq(s->irq, 0);
stm32f2xx_update_irq(s);
}
static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
@ -106,7 +115,7 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
retvalue = s->usart_dr & 0x3FF;
s->usart_sr &= ~USART_SR_RXNE;
qemu_chr_fe_accept_input(&s->chr);
qemu_set_irq(s->irq, 0);
stm32f2xx_update_irq(s);
return retvalue;
case USART_BRR:
return s->usart_brr;
@ -145,9 +154,7 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
} else {
s->usart_sr &= value;
}
if (!(s->usart_sr & USART_SR_RXNE)) {
qemu_set_irq(s->irq, 0);
}
stm32f2xx_update_irq(s);
return;
case USART_DR:
if (value < 0xF000) {
@ -161,6 +168,7 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
clear TC by writing 0 to the SR register, so set it again
on each write. */
s->usart_sr |= USART_SR_TC;
stm32f2xx_update_irq(s);
}
return;
case USART_BRR:
@ -168,10 +176,7 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
return;
case USART_CR1:
s->usart_cr1 = value;
if (s->usart_cr1 & USART_CR1_RXNEIE &&
s->usart_sr & USART_SR_RXNE) {
qemu_set_irq(s->irq, 1);
}
stm32f2xx_update_irq(s);
return;
case USART_CR2:
s->usart_cr2 = value;

21
hw/core/qdev-properties.c
View file

@ -3,12 +3,14 @@
#include "qapi/error.h"
#include "qapi/qapi-types-misc.h"
#include "qapi/qmp/qerror.h"
#include "qapi/qmp/qlist.h"
#include "qemu/ctype.h"
#include "qemu/error-report.h"
#include "qapi/visitor.h"
#include "qemu/units.h"
#include "qemu/cutils.h"
#include "qdev-prop-internal.h"
#include "qom/qom-qobject.h"
void qdev_prop_set_after_realize(DeviceState *dev, const char *name,
Error **errp)
@ -739,6 +741,25 @@ void qdev_prop_set_enum(DeviceState *dev, const char *name, int value)
&error_abort);
}
void qdev_prop_set_array(DeviceState *dev, const char *name, QList *values)
{
const QListEntry *entry;
g_autofree char *prop_len = g_strdup_printf("len-%s", name);
uint32_t i = 0;
object_property_set_int(OBJECT(dev), prop_len, qlist_size(values),
&error_abort);
QLIST_FOREACH_ENTRY(values, entry) {
g_autofree char *prop_idx = g_strdup_printf("%s[%u]", name, i);
object_property_set_qobject(OBJECT(dev), prop_idx, entry->value,
&error_abort);
i++;
}
qobject_unref(values);
}
static GPtrArray *global_props(void)
{
static GPtrArray *gp;

2
hw/display/vga-isa.c
View file

@ -1,7 +1,7 @@
/*
* QEMU ISA VGA Emulator.
*
* see docs/specs/standard-vga.txt for virtual hardware specs.
* see docs/specs/standard-vga.rst for virtual hardware specs.
*
* Copyright (c) 2003 Fabrice Bellard
*

2
hw/display/vga-pci.c
View file

@ -1,7 +1,7 @@
/*
* QEMU PCI VGA Emulator.
*
* see docs/specs/standard-vga.txt for virtual hardware specs.
* see docs/specs/standard-vga.rst for virtual hardware specs.
*
* Copyright (c) 2003 Fabrice Bellard
*

18
hw/i2c/pm_smbus.c
View file

@ -23,6 +23,7 @@
#include "hw/i2c/pm_smbus.h"
#include "hw/i2c/smbus_master.h"
#include "migration/vmstate.h"
#include "trace.h"
#define SMBHSTSTS 0x00
#define SMBHSTCNT 0x02
@ -64,15 +65,6 @@
#define AUX_BLK (1 << 1)
#define AUX_MASK 0x3
/*#define DEBUG*/
#ifdef DEBUG
# define SMBUS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
#else
# define SMBUS_DPRINTF(format, ...) do { } while (0)
#endif
static void smb_transaction(PMSMBus *s)
{
uint8_t prot = (s->smb_ctl >> 2) & 0x07;
@ -82,7 +74,7 @@ static void smb_transaction(PMSMBus *s)
I2CBus *bus = s->smbus;
int ret;
SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
trace_smbus_transaction(addr, prot);
/* Transaction isn't exec if STS_DEV_ERR bit set */
if ((s->smb_stat & STS_DEV_ERR) != 0) {
goto error;
@ -258,8 +250,7 @@ static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
PMSMBus *s = opaque;
uint8_t clear_byte_done;
SMBUS_DPRINTF("SMB writeb port=0x%04" HWADDR_PRIx
" val=0x%02" PRIx64 "\n", addr, val);
trace_smbus_ioport_writeb(addr, val);
switch(addr) {
case SMBHSTSTS:
clear_byte_done = s->smb_stat & val & STS_BYTE_DONE;
@ -429,8 +420,7 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width)
val = 0;
break;
}
SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n",
addr, val);
trace_smbus_ioport_readb(addr, val);
if (s->set_irq) {
s->set_irq(s, smb_irq_value(s));

6
hw/i2c/trace-events
View file

@ -15,6 +15,12 @@ i2c_send_async(uint8_t address, uint8_t data) "send_async(addr:0x%02x) data:0x%0
i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x"
i2c_ack(void) ""
# pm_smbus.c
smbus_ioport_readb(uint16_t addr, uint8_t data) "[0x%04" PRIx16 "] -> val=0x%02x"
smbus_ioport_writeb(uint16_t addr, uint8_t data) "[0x%04" PRIx16 "] <- val=0x%02x"
smbus_transaction(uint8_t addr, uint8_t prot) "addr=0x%02x prot=0x%02x"
# allwinner_i2c.c
allwinner_i2c_read(const char* reg_name, uint64_t offset, uint64_t value) "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64

2
hw/input/Kconfig
View file

@ -20,7 +20,7 @@ config PL050
config PS2
bool
config STELLARIS_INPUT
config STELLARIS_GAMEPAD
bool
config TSC2005

2
hw/input/meson.build
View file

@ -5,7 +5,7 @@ system_ss.add(when: 'CONFIG_LM832X', if_true: files('lm832x.c'))
system_ss.add(when: 'CONFIG_PCKBD', if_true: files('pckbd.c'))
system_ss.add(when: 'CONFIG_PL050', if_true: files('pl050.c'))
system_ss.add(when: 'CONFIG_PS2', if_true: files('ps2.c'))
system_ss.add(when: 'CONFIG_STELLARIS_INPUT', if_true: files('stellaris_input.c'))
system_ss.add(when: 'CONFIG_STELLARIS_GAMEPAD', if_true: files('stellaris_gamepad.c'))
system_ss.add(when: 'CONFIG_TSC2005', if_true: files('tsc2005.c'))
system_ss.add(when: 'CONFIG_VIRTIO_INPUT', if_true: files('virtio-input.c'))

99
hw/input/stellaris_gamepad.c Normal file
View file

@ -0,0 +1,99 @@
/*
* Gamepad style buttons connected to IRQ/GPIO lines
*
* Copyright (c) 2007 CodeSourcery.
* Written by Paul Brook
*
* This code is licensed under the GPL.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/input/stellaris_gamepad.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "ui/console.h"
static void stellaris_gamepad_event(DeviceState *dev, QemuConsole *src,
InputEvent *evt)
{
StellarisGamepad *s = STELLARIS_GAMEPAD(dev);
InputKeyEvent *key = evt->u.key.data;
int qcode = qemu_input_key_value_to_qcode(key->key);
int i;
for (i = 0; i < s->num_buttons; i++) {
if (s->keycodes[i] == qcode && s->pressed[i] != key->down) {
s->pressed[i] = key->down;
qemu_set_irq(s->irqs[i], key->down);
}
}
}
static const VMStateDescription vmstate_stellaris_gamepad = {
.name = "stellaris_gamepad",
.version_id = 4,
.minimum_version_id = 4,
.fields = (VMStateField[]) {
VMSTATE_VARRAY_UINT32(pressed, StellarisGamepad, num_buttons,
0, vmstate_info_uint8, uint8_t),
VMSTATE_END_OF_LIST()
}
};
static const QemuInputHandler stellaris_gamepad_handler = {
.name = "Stellaris Gamepad",
.mask = INPUT_EVENT_MASK_KEY,
.event = stellaris_gamepad_event,
};
static void stellaris_gamepad_realize(DeviceState *dev, Error **errp)
{
StellarisGamepad *s = STELLARIS_GAMEPAD(dev);
if (s->num_buttons == 0) {
error_setg(errp, "keycodes property array must be set");
return;
}
s->irqs = g_new0(qemu_irq, s->num_buttons);
s->pressed = g_new0(uint8_t, s->num_buttons);
qdev_init_gpio_out(dev, s->irqs, s->num_buttons);
qemu_input_handler_register(dev, &stellaris_gamepad_handler);
}
static void stellaris_gamepad_reset_enter(Object *obj, ResetType type)
{
StellarisGamepad *s = STELLARIS_GAMEPAD(obj);
memset(s->pressed, 0, s->num_buttons * sizeof(uint8_t));
}
static Property stellaris_gamepad_properties[] = {
DEFINE_PROP_ARRAY("keycodes", StellarisGamepad, num_buttons,
keycodes, qdev_prop_uint32, uint32_t),
DEFINE_PROP_END_OF_LIST(),
};
static void stellaris_gamepad_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
rc->phases.enter = stellaris_gamepad_reset_enter;
dc->realize = stellaris_gamepad_realize;
dc->vmsd = &vmstate_stellaris_gamepad;
device_class_set_props(dc, stellaris_gamepad_properties);
}
static const TypeInfo stellaris_gamepad_info[] = {
{
.name = TYPE_STELLARIS_GAMEPAD,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StellarisGamepad),
.class_init = stellaris_gamepad_class_init,
},
};
DEFINE_TYPES(stellaris_gamepad_info);

92
hw/input/stellaris_input.c
View file

@ -1,92 +0,0 @@
/*
* Gamepad style buttons connected to IRQ/GPIO lines
*
* Copyright (c) 2007 CodeSourcery.
* Written by Paul Brook
*
* This code is licensed under the GPL.
*/
#include "qemu/osdep.h"
#include "hw/input/gamepad.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "ui/console.h"
typedef struct {
qemu_irq irq;
int keycode;
uint8_t pressed;
} gamepad_button;
typedef struct {
gamepad_button *buttons;
int num_buttons;
int extension;
} gamepad_state;
static void stellaris_gamepad_put_key(void * opaque, int keycode)
{
gamepad_state *s = (gamepad_state *)opaque;
int i;
int down;
if (keycode == 0xe0 && !s->extension) {
s->extension = 0x80;
return;
}
down = (keycode & 0x80) == 0;
keycode = (keycode & 0x7f) | s->extension;
for (i = 0; i < s->num_buttons; i++) {
if (s->buttons[i].keycode == keycode
&& s->buttons[i].pressed != down) {
s->buttons[i].pressed = down;
qemu_set_irq(s->buttons[i].irq, down);
}
}
s->extension = 0;
}
static const VMStateDescription vmstate_stellaris_button = {
.name = "stellaris_button",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT8(pressed, gamepad_button),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_stellaris_gamepad = {
.name = "stellaris_gamepad",
.version_id = 2,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_INT32(extension, gamepad_state),
VMSTATE_STRUCT_VARRAY_POINTER_INT32(buttons, gamepad_state,
num_buttons,
vmstate_stellaris_button,
gamepad_button),
VMSTATE_END_OF_LIST()
}
};
/* Returns an array of 5 output slots. */
void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode)
{
gamepad_state *s;
int i;
s = g_new0(gamepad_state, 1);
s->buttons = g_new0(gamepad_button, n);
for (i = 0; i < n; i++) {
s->buttons[i].irq = irq[i];
s->buttons[i].keycode = keycode[i];
}
s->num_buttons = n;
qemu_add_kbd_event_handler(stellaris_gamepad_put_key, s);
vmstate_register_any(NULL, &vmstate_stellaris_gamepad, s);
}

3
hw/misc/Kconfig
View file

@ -197,4 +197,7 @@ config DJMEMC
config IOSB
bool
config XLNX_VERSAL_TRNG
bool
source macio/Kconfig

41
hw/misc/imx6_ccm.c
View file

@ -15,18 +15,7 @@
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
#ifndef DEBUG_IMX6_CCM
#define DEBUG_IMX6_CCM 0
#endif
#define DPRINTF(fmt, args...) \
do { \
if (DEBUG_IMX6_CCM) { \
fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX6_CCM, \
__func__, ##args); \
} \
} while (0)
#include "trace.h"
static const char *imx6_ccm_reg_name(uint32_t reg)
{
@ -263,7 +252,7 @@ static uint64_t imx6_analog_get_pll2_clk(IMX6CCMState *dev)
freq *= 20;
}
DPRINTF("freq = %u\n", (uint32_t)freq);
trace_imx6_analog_get_pll2_clk(freq);
return freq;
}
@ -275,7 +264,7 @@ static uint64_t imx6_analog_get_pll2_pfd0_clk(IMX6CCMState *dev)
freq = imx6_analog_get_pll2_clk(dev) * 18
/ EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD0_FRAC);
DPRINTF("freq = %u\n", (uint32_t)freq);
trace_imx6_analog_get_pll2_pfd0_clk(freq);
return freq;
}
@ -287,7 +276,7 @@ static uint64_t imx6_analog_get_pll2_pfd2_clk(IMX6CCMState *dev)
freq = imx6_analog_get_pll2_clk(dev) * 18
/ EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD2_FRAC);
DPRINTF("freq = %u\n", (uint32_t)freq);
trace_imx6_analog_get_pll2_pfd2_clk(freq);
return freq;
}
@ -315,7 +304,7 @@ static uint64_t imx6_analog_get_periph_clk(IMX6CCMState *dev)
break;
}
DPRINTF("freq = %u\n", (uint32_t)freq);
trace_imx6_analog_get_periph_clk(freq);
return freq;
}
@ -327,7 +316,7 @@ static uint64_t imx6_ccm_get_ahb_clk(IMX6CCMState *dev)
freq = imx6_analog_get_periph_clk(dev)
/ (1 + EXTRACT(dev->ccm[CCM_CBCDR], AHB_PODF));
DPRINTF("freq = %u\n", (uint32_t)freq);
trace_imx6_ccm_get_ahb_clk(freq);
return freq;
}
@ -339,7 +328,7 @@ static uint64_t imx6_ccm_get_ipg_clk(IMX6CCMState *dev)
freq = imx6_ccm_get_ahb_clk(dev)
/ (1 + EXTRACT(dev->ccm[CCM_CBCDR], IPG_PODF));
DPRINTF("freq = %u\n", (uint32_t)freq);
trace_imx6_ccm_get_ipg_clk(freq);
return freq;
}
@ -351,7 +340,7 @@ static uint64_t imx6_ccm_get_per_clk(IMX6CCMState *dev)
freq = imx6_ccm_get_ipg_clk(dev)
/ (1 + EXTRACT(dev->ccm[CCM_CSCMR1], PERCLK_PODF));
DPRINTF("freq = %u\n", (uint32_t)freq);
trace_imx6_ccm_get_per_clk(freq);
return freq;
}
@ -385,7 +374,7 @@ static uint32_t imx6_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
break;
}
DPRINTF("Clock = %d) = %u\n", clock, freq);
trace_imx6_ccm_get_clock_frequency(clock, freq);
return freq;
}
@ -394,7 +383,7 @@ static void imx6_ccm_reset(DeviceState *dev)
{
IMX6CCMState *s = IMX6_CCM(dev);
DPRINTF("\n");
trace_imx6_ccm_reset();
s->ccm[CCM_CCR] = 0x040116FF;
s->ccm[CCM_CCDR] = 0x00000000;
@ -483,7 +472,7 @@ static uint64_t imx6_ccm_read(void *opaque, hwaddr offset, unsigned size)
value = s->ccm[index];
DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx6_ccm_reg_name(index), value);
trace_imx6_ccm_read(imx6_ccm_reg_name(index), value);
return (uint64_t)value;
}
@ -494,8 +483,7 @@ static void imx6_ccm_write(void *opaque, hwaddr offset, uint64_t value,
uint32_t index = offset >> 2;
IMX6CCMState *s = (IMX6CCMState *)opaque;
DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx6_ccm_reg_name(index),
(uint32_t)value);
trace_imx6_ccm_write(imx6_ccm_reg_name(index), (uint32_t)value);
/*
* We will do a better implementation later. In particular some bits
@ -591,7 +579,7 @@ static uint64_t imx6_analog_read(void *opaque, hwaddr offset, unsigned size)
break;
}
DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx6_analog_reg_name(index), value);
trace_imx6_analog_read(imx6_analog_reg_name(index), value);
return (uint64_t)value;
}
@ -602,8 +590,7 @@ static void imx6_analog_write(void *opaque, hwaddr offset, uint64_t value,
uint32_t index = offset >> 2;
IMX6CCMState *s = (IMX6CCMState *)opaque;
DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx6_analog_reg_name(index),
(uint32_t)value);
trace_imx6_analog_write(imx6_analog_reg_name(index), (uint32_t)value);
switch (index) {
case CCM_ANALOG_PLL_ARM_SET:

5
hw/misc/imx7_snvs.c
View file

@ -16,9 +16,12 @@
#include "hw/misc/imx7_snvs.h"
#include "qemu/module.h"
#include "sysemu/runstate.h"
#include "trace.h"
static uint64_t imx7_snvs_read(void *opaque, hwaddr offset, unsigned size)
{
trace_imx7_snvs_read(offset, 0);
return 0;
}
@ -28,6 +31,8 @@ static void imx7_snvs_write(void *opaque, hwaddr offset,
const uint32_t value = v;
const uint32_t mask = SNVS_LPCR_TOP | SNVS_LPCR_DP_EN;
trace_imx7_snvs_write(offset, value);
if (offset == SNVS_LPCR && ((value & mask) == mask)) {
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
}

3
hw/misc/meson.build
View file

@ -104,6 +104,9 @@ system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
'xlnx-cfi-if.c',
'xlnx-versal-cframe-reg.c',
))
system_ss.add(when: 'CONFIG_XLNX_VERSAL_TRNG', if_true: files(
'xlnx-versal-trng.c',
))
system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
system_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c'))

19
hw/misc/trace-events
View file

@ -115,6 +115,10 @@ msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status regist
imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64
imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64
# imx7_snvs.c
imx7_snvs_read(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx32
imx7_snvs_write(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx32
# mos6522.c
mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d"
mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64
@ -192,6 +196,21 @@ iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit Sec
iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u"
iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u"
# imx6_ccm.c
imx6_analog_get_periph_clk(uint32_t freq) "freq = %u Hz"
imx6_analog_get_pll2_clk(uint32_t freq) "freq = %u Hz"
imx6_analog_get_pll2_pfd0_clk(uint32_t freq) "freq = %u Hz"
imx6_analog_get_pll2_pfd2_clk(uint32_t freq) "freq = %u Hz"
imx6_analog_read(const char *reg, uint32_t value) "reg[%s] => 0x%" PRIx32
imx6_analog_write(const char *reg, uint32_t value) "reg[%s] <= 0x%" PRIx32
imx6_ccm_get_ahb_clk(uint32_t freq) "freq = %u Hz"
imx6_ccm_get_ipg_clk(uint32_t freq) "freq = %u Hz"
imx6_ccm_get_per_clk(uint32_t freq) "freq = %u Hz"
imx6_ccm_get_clock_frequency(unsigned clock, uint32_t freq) "(Clock = %d) = %u"
imx6_ccm_read(const char *reg, uint32_t value) "reg[%s] => 0x%" PRIx32
imx6_ccm_reset(void) ""
imx6_ccm_write(const char *reg, uint32_t value) "reg[%s] <= 0x%" PRIx32
# imx6ul_ccm.c
ccm_entry(void) ""
ccm_freq(uint32_t freq) "freq = %d"

717
hw/misc/xlnx-versal-trng.c Normal file
View file

@ -0,0 +1,717 @@
/*
* Non-crypto strength model of the True Random Number Generator
* in the AMD/Xilinx Versal device family.
*
* Copyright (c) 2017-2020 Xilinx Inc.
* Copyright (c) 2023 Advanced Micro Devices, Inc.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "hw/misc/xlnx-versal-trng.h"
#include "qemu/bitops.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qemu/guest-random.h"
#include "qemu/timer.h"
#include "qapi/visitor.h"
#include "migration/vmstate.h"
#include "hw/qdev-properties.h"
#ifndef XLNX_VERSAL_TRNG_ERR_DEBUG
#define XLNX_VERSAL_TRNG_ERR_DEBUG 0
#endif
REG32(INT_CTRL, 0x0)
FIELD(INT_CTRL, CERTF_RST, 5, 1)
FIELD(INT_CTRL, DTF_RST, 4, 1)
FIELD(INT_CTRL, DONE_RST, 3, 1)
FIELD(INT_CTRL, CERTF_EN, 2, 1)
FIELD(INT_CTRL, DTF_EN, 1, 1)
FIELD(INT_CTRL, DONE_EN, 0, 1)
REG32(STATUS, 0x4)
FIELD(STATUS, QCNT, 9, 3)
FIELD(STATUS, EAT, 4, 5)
FIELD(STATUS, CERTF, 3, 1)
FIELD(STATUS, DTF, 1, 1)
FIELD(STATUS, DONE, 0, 1)
REG32(CTRL, 0x8)
FIELD(CTRL, PERSODISABLE, 10, 1)
FIELD(CTRL, SINGLEGENMODE, 9, 1)
FIELD(CTRL, EUMODE, 8, 1)
FIELD(CTRL, PRNGMODE, 7, 1)
FIELD(CTRL, TSTMODE, 6, 1)
FIELD(CTRL, PRNGSTART, 5, 1)
FIELD(CTRL, EATAU, 4, 1)
FIELD(CTRL, PRNGXS, 3, 1)
FIELD(CTRL, TRSSEN, 2, 1)
FIELD(CTRL, QERTUEN, 1, 1)
FIELD(CTRL, PRNGSRST, 0, 1)
REG32(CTRL_2, 0xc)
FIELD(CTRL_2, REPCOUNTTESTCUTOFF, 8, 9)
FIELD(CTRL_2, RESERVED_7_5, 5, 3)
FIELD(CTRL_2, DIT, 0, 5)
REG32(CTRL_3, 0x10)
FIELD(CTRL_3, ADAPTPROPTESTCUTOFF, 8, 10)
FIELD(CTRL_3, DLEN, 0, 8)
REG32(CTRL_4, 0x14)
FIELD(CTRL_4, SINGLEBITRAW, 0, 1)
REG32(EXT_SEED_0, 0x40)
REG32(EXT_SEED_1, 0x44)
REG32(EXT_SEED_2, 0x48)
REG32(EXT_SEED_3, 0x4c)
REG32(EXT_SEED_4, 0x50)
REG32(EXT_SEED_5, 0x54)
REG32(EXT_SEED_6, 0x58)
REG32(EXT_SEED_7, 0x5c)
REG32(EXT_SEED_8, 0x60)
REG32(EXT_SEED_9, 0x64)
REG32(EXT_SEED_10, 0x68)
REG32(EXT_SEED_11, 0x6c)
REG32(PER_STRNG_0, 0x80)
REG32(PER_STRNG_1, 0x84)
REG32(PER_STRNG_2, 0x88)
REG32(PER_STRNG_3, 0x8c)
REG32(PER_STRNG_4, 0x90)
REG32(PER_STRNG_5, 0x94)
REG32(PER_STRNG_6, 0x98)
REG32(PER_STRNG_7, 0x9c)
REG32(PER_STRNG_8, 0xa0)
REG32(PER_STRNG_9, 0xa4)
REG32(PER_STRNG_10, 0xa8)
REG32(PER_STRNG_11, 0xac)
REG32(CORE_OUTPUT, 0xc0)
REG32(RESET, 0xd0)
FIELD(RESET, VAL, 0, 1)
REG32(OSC_EN, 0xd4)
FIELD(OSC_EN, VAL, 0, 1)
REG32(TRNG_ISR, 0xe0)
FIELD(TRNG_ISR, SLVERR, 1, 1)
FIELD(TRNG_ISR, CORE_INT, 0, 1)
REG32(TRNG_IMR, 0xe4)
FIELD(TRNG_IMR, SLVERR, 1, 1)
FIELD(TRNG_IMR, CORE_INT, 0, 1)
REG32(TRNG_IER, 0xe8)
FIELD(TRNG_IER, SLVERR, 1, 1)
FIELD(TRNG_IER, CORE_INT, 0, 1)
REG32(TRNG_IDR, 0xec)
FIELD(TRNG_IDR, SLVERR, 1, 1)
FIELD(TRNG_IDR, CORE_INT, 0, 1)
REG32(SLV_ERR_CTRL, 0xf0)
FIELD(SLV_ERR_CTRL, ENABLE, 0, 1)
#define R_MAX (R_SLV_ERR_CTRL + 1)
QEMU_BUILD_BUG_ON(R_MAX * 4 != sizeof_field(XlnxVersalTRng, regs));
#define TRNG_GUEST_ERROR(D, FMT, ...) \
do { \
g_autofree char *p = object_get_canonical_path(OBJECT(D)); \
qemu_log_mask(LOG_GUEST_ERROR, "%s: " FMT, p, ## __VA_ARGS__); \
} while (0)
#define TRNG_WARN(D, FMT, ...) \
do { \
g_autofree char *p = object_get_canonical_path(OBJECT(D)); \
warn_report("%s: " FMT, p, ## __VA_ARGS__); \
} while (0)
static bool trng_older_than_v2(XlnxVersalTRng *s)
{
return s->hw_version < 0x0200;
}
static bool trng_in_reset(XlnxVersalTRng *s)
{
if (ARRAY_FIELD_EX32(s->regs, RESET, VAL)) {
return true;
}
if (ARRAY_FIELD_EX32(s->regs, CTRL, PRNGSRST)) {
return true;
}
return false;
}
static bool trng_test_enabled(XlnxVersalTRng *s)
{
return ARRAY_FIELD_EX32(s->regs, CTRL, TSTMODE);
}
static bool trng_trss_enabled(XlnxVersalTRng *s)
{
if (trng_in_reset(s)) {
return false;
}
if (!ARRAY_FIELD_EX32(s->regs, CTRL, TRSSEN)) {
return false;
}
if (!ARRAY_FIELD_EX32(s->regs, OSC_EN, VAL)) {
return false;
}
return true;
}
static void trng_seed_128(uint32_t *seed, uint64_t h00, uint64_t h64)
{
seed[0] = extract64(h00, 0, 32);
seed[1] = extract64(h00, 32, 32);
seed[2] = extract64(h64, 0, 32);
seed[3] = extract64(h64, 32, 32);
}
static void trng_reseed(XlnxVersalTRng *s)
{
bool ext_seed = ARRAY_FIELD_EX32(s->regs, CTRL, PRNGXS);
bool pers_disabled = ARRAY_FIELD_EX32(s->regs, CTRL, PERSODISABLE);
enum {
U384_U8 = 384 / 8,
U384_U32 = 384 / 32,
};
/*
* Maximum seed length is len(personalized string) + len(ext seed).
*
* g_rand_set_seed_array() takes array of uint32 in host endian.
*/
guint32 gs[U384_U32 * 2], *seed = &gs[U384_U32];
/*
* A disabled personalized string is the same as
* a string with all zeros.
*
* The device's hardware spec defines 3 modes (all selectable
* by guest at will and at anytime):
* 1) External seeding
* This is a PRNG mode, in which the produced sequence shall
* be reproducible if reseeded by the same 384-bit seed, as
* supplied by guest software.
* 2) Test seeding
* This is a PRNG mode, in which the produced sequence shall
* be reproducible if reseeded by a 128-bit test seed, as
* supplied by guest software.
* 3) Truly-random seeding
* This is the TRNG mode, in which the produced sequence is
* periodically reseeded by a crypto-strength entropy source.
*
* To assist debugging of certain classes of software defects,
* this QEMU model implements a 4th mode,
* 4) Forced PRNG
* When in this mode, a reproducible sequence is generated
* if software has selected the TRNG mode (mode 2).
*
* This emulation-only mode can only be selected by setting
* the uint64 property 'forced-prng' to a non-zero value.
* Guest software cannot select this mode.
*/
memset(gs, 0, sizeof(gs));
if (!pers_disabled) {
memcpy(gs, &s->regs[R_PER_STRNG_0], U384_U8);
}
if (ext_seed) {
memcpy(seed, &s->regs[R_EXT_SEED_0], U384_U8);
} else if (trng_test_enabled(s)) {
trng_seed_128(seed, s->tst_seed[0], s->tst_seed[1]);
} else if (s->forced_prng_seed) {
s->forced_prng_count++;
trng_seed_128(seed, s->forced_prng_count, s->forced_prng_seed);
} else {
qemu_guest_getrandom_nofail(seed, U384_U8);
}
g_rand_set_seed_array(s->prng, gs, ARRAY_SIZE(gs));
s->rand_count = 0;
s->rand_reseed = 1ULL << 48;
}
static void trng_regen(XlnxVersalTRng *s)
{
if (s->rand_reseed == 0) {
TRNG_GUEST_ERROR(s, "Too many generations without a reseed");
trng_reseed(s);
}
s->rand_reseed--;
/*
* In real hardware, each regen creates 256 bits, but QCNT
* reports a max of 4.
*/
ARRAY_FIELD_DP32(s->regs, STATUS, QCNT, 4);
s->rand_count = 256 / 32;
}
static uint32_t trng_rdout(XlnxVersalTRng *s)
{
assert(s->rand_count);
s->rand_count--;
if (s->rand_count < 4) {
ARRAY_FIELD_DP32(s->regs, STATUS, QCNT, s->rand_count);
}
return g_rand_int(s->prng);
}
static void trng_irq_update(XlnxVersalTRng *s)
{
bool pending = s->regs[R_TRNG_ISR] & ~s->regs[R_TRNG_IMR];
qemu_set_irq(s->irq, pending);
}
static void trng_isr_postw(RegisterInfo *reg, uint64_t val64)
{
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
trng_irq_update(s);
}
static uint64_t trng_ier_prew(RegisterInfo *reg, uint64_t val64)
{
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
uint32_t val = val64;
s->regs[R_TRNG_IMR] &= ~val;
trng_irq_update(s);
return 0;
}
static uint64_t trng_idr_prew(RegisterInfo *reg, uint64_t val64)
{
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
uint32_t val = val64;
s->regs[R_TRNG_IMR] |= val;
trng_irq_update(s);
return 0;
}
static void trng_core_int_update(XlnxVersalTRng *s)
{
bool pending = false;
uint32_t st = s->regs[R_STATUS];
uint32_t en = s->regs[R_INT_CTRL];
if (FIELD_EX32(st, STATUS, CERTF) && FIELD_EX32(en, INT_CTRL, CERTF_EN)) {
pending = true;
}
if (FIELD_EX32(st, STATUS, DTF) && FIELD_EX32(en, INT_CTRL, DTF_EN)) {
pending = true;
}
if (FIELD_EX32(st, STATUS, DONE) && FIELD_EX32(en, INT_CTRL, DONE_EN)) {
pending = true;
}
ARRAY_FIELD_DP32(s->regs, TRNG_ISR, CORE_INT, pending);
trng_irq_update(s);
}
static void trng_int_ctrl_postw(RegisterInfo *reg, uint64_t val64)
{
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
uint32_t v32 = val64;
uint32_t clr_mask = 0;
if (FIELD_EX32(v32, INT_CTRL, CERTF_RST)) {
clr_mask |= R_STATUS_CERTF_MASK;
}
if (FIELD_EX32(v32, INT_CTRL, DTF_RST)) {
clr_mask |= R_STATUS_DTF_MASK;
}
if (FIELD_EX32(v32, INT_CTRL, DONE_RST)) {
clr_mask |= R_STATUS_DONE_MASK;
}
s->regs[R_STATUS] &= ~clr_mask;
trng_core_int_update(s);
}
static void trng_done(XlnxVersalTRng *s)
{
ARRAY_FIELD_DP32(s->regs, STATUS, DONE, true);
trng_core_int_update(s);
}
static void trng_fault_event_set(XlnxVersalTRng *s, uint32_t events)
{
bool pending = false;
/* Disabled TRSS cannot generate any fault event */
if (!trng_trss_enabled(s)) {
return;
}
if (FIELD_EX32(events, STATUS, CERTF)) {
/* In older version, ERTU must be enabled explicitly to get CERTF */
if (trng_older_than_v2(s) &&
!ARRAY_FIELD_EX32(s->regs, CTRL, QERTUEN)) {
TRNG_WARN(s, "CERTF injection ignored: ERTU disabled");
} else {
ARRAY_FIELD_DP32(s->regs, STATUS, CERTF, true);
pending = true;
}
}
if (FIELD_EX32(events, STATUS, DTF)) {
ARRAY_FIELD_DP32(s->regs, STATUS, DTF, true);
pending = true;
}
if (pending) {
trng_core_int_update(s);
}
}
static void trng_soft_reset(XlnxVersalTRng *s)
{
s->rand_count = 0;
s->regs[R_STATUS] = 0;
ARRAY_FIELD_DP32(s->regs, TRNG_ISR, CORE_INT, 0);
}
static void trng_ctrl_postw(RegisterInfo *reg, uint64_t val64)
{
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
if (trng_in_reset(s)) {
return;
}
if (FIELD_EX32(val64, CTRL, PRNGSRST)) {
trng_soft_reset(s);
trng_irq_update(s);
return;
}
if (!FIELD_EX32(val64, CTRL, PRNGSTART)) {
return;
}
if (FIELD_EX32(val64, CTRL, PRNGMODE)) {
trng_regen(s);
} else {
trng_reseed(s);
}
trng_done(s);
}
static void trng_ctrl4_postw(RegisterInfo *reg, uint64_t val64)
{
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
/* Only applies to test mode with TRSS enabled */
if (!trng_test_enabled(s) || !trng_trss_enabled(s)) {
return;
}
/* Shift in a single bit. */
s->tst_seed[1] <<= 1;
s->tst_seed[1] |= s->tst_seed[0] >> 63;
s->tst_seed[0] <<= 1;
s->tst_seed[0] |= val64 & 1;
trng_reseed(s);
trng_regen(s);
}
static uint64_t trng_core_out_postr(RegisterInfo *reg, uint64_t val)
{
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
bool oneshot = ARRAY_FIELD_EX32(s->regs, CTRL, SINGLEGENMODE);
bool start = ARRAY_FIELD_EX32(s->regs, CTRL, PRNGSTART);
uint32_t r = 0xbad;
if (trng_in_reset(s)) {
TRNG_GUEST_ERROR(s, "Reading random number while in reset!");
return r;
}
if (s->rand_count == 0) {
TRNG_GUEST_ERROR(s, "Reading random number when unavailable!");
return r;
}
r = trng_rdout(s);
/* Automatic mode regenerates when half the output reg is empty. */
if (!oneshot && start && s->rand_count <= 3) {
trng_regen(s);
}
return r;
}
static void trng_reset(XlnxVersalTRng *s)
{
unsigned int i;
s->forced_prng_count = 0;
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
register_reset(&s->regs_info[i]);
}
trng_soft_reset(s);
trng_irq_update(s);
}
static uint64_t trng_reset_prew(RegisterInfo *reg, uint64_t val64)
{
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
if (!ARRAY_FIELD_EX32(s->regs, RESET, VAL) &&
FIELD_EX32(val64, RESET, VAL)) {
trng_reset(s);
}
return val64;
}
static uint64_t trng_register_read(void *opaque, hwaddr addr, unsigned size)
{
/*
* Guest provided seed and personalized strings cannot be
* read back, and read attempts return value of A_STATUS.
*/
switch (addr) {
case A_EXT_SEED_0 ... A_PER_STRNG_11:
addr = A_STATUS;
break;
}
return register_read_memory(opaque, addr, size);
}
static void trng_register_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
RegisterInfoArray *reg_array = opaque;
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg_array->r[0]->opaque);
if (trng_older_than_v2(s)) {
switch (addr) {
case A_CTRL:
value = FIELD_DP64(value, CTRL, PERSODISABLE, 0);
value = FIELD_DP64(value, CTRL, SINGLEGENMODE, 0);
break;
case A_CTRL_2:
case A_CTRL_3:
case A_CTRL_4:
return;
}
} else {
switch (addr) {
case A_CTRL:
value = FIELD_DP64(value, CTRL, EATAU, 0);
value = FIELD_DP64(value, CTRL, QERTUEN, 0);
break;
}
}
register_write_memory(opaque, addr, value, size);
}
static RegisterAccessInfo trng_regs_info[] = {
{ .name = "INT_CTRL", .addr = A_INT_CTRL,
.post_write = trng_int_ctrl_postw,
},{ .name = "STATUS", .addr = A_STATUS,
.ro = 0xfff,
},{ .name = "CTRL", .addr = A_CTRL,
.post_write = trng_ctrl_postw,
},{ .name = "CTRL_2", .addr = A_CTRL_2,
.reset = 0x210c,
},{ .name = "CTRL_3", .addr = A_CTRL_3,
.reset = 0x26f09,
},{ .name = "CTRL_4", .addr = A_CTRL_4,
.post_write = trng_ctrl4_postw,
},{ .name = "EXT_SEED_0", .addr = A_EXT_SEED_0,
},{ .name = "EXT_SEED_1", .addr = A_EXT_SEED_1,
},{ .name = "EXT_SEED_2", .addr = A_EXT_SEED_2,
},{ .name = "EXT_SEED_3", .addr = A_EXT_SEED_3,
},{ .name = "EXT_SEED_4", .addr = A_EXT_SEED_4,
},{ .name = "EXT_SEED_5", .addr = A_EXT_SEED_5,
},{ .name = "EXT_SEED_6", .addr = A_EXT_SEED_6,
},{ .name = "EXT_SEED_7", .addr = A_EXT_SEED_7,
},{ .name = "EXT_SEED_8", .addr = A_EXT_SEED_8,
},{ .name = "EXT_SEED_9", .addr = A_EXT_SEED_9,
},{ .name = "EXT_SEED_10", .addr = A_EXT_SEED_10,
},{ .name = "EXT_SEED_11", .addr = A_EXT_SEED_11,
},{ .name = "PER_STRNG_0", .addr = A_PER_STRNG_0,
},{ .name = "PER_STRNG_1", .addr = A_PER_STRNG_1,
},{ .name = "PER_STRNG_2", .addr = A_PER_STRNG_2,
},{ .name = "PER_STRNG_3", .addr = A_PER_STRNG_3,
},{ .name = "PER_STRNG_4", .addr = A_PER_STRNG_4,
},{ .name = "PER_STRNG_5", .addr = A_PER_STRNG_5,
},{ .name = "PER_STRNG_6", .addr = A_PER_STRNG_6,
},{ .name = "PER_STRNG_7", .addr = A_PER_STRNG_7,
},{ .name = "PER_STRNG_8", .addr = A_PER_STRNG_8,
},{ .name = "PER_STRNG_9", .addr = A_PER_STRNG_9,
},{ .name = "PER_STRNG_10", .addr = A_PER_STRNG_10,
},{ .name = "PER_STRNG_11", .addr = A_PER_STRNG_11,
},{ .name = "CORE_OUTPUT", .addr = A_CORE_OUTPUT,
.ro = 0xffffffff,
.post_read = trng_core_out_postr,
},{ .name = "RESET", .addr = A_RESET,
.reset = 0x1,
.pre_write = trng_reset_prew,
},{ .name = "OSC_EN", .addr = A_OSC_EN,
},{ .name = "TRNG_ISR", .addr = A_TRNG_ISR,
.w1c = 0x3,
.post_write = trng_isr_postw,
},{ .name = "TRNG_IMR", .addr = A_TRNG_IMR,
.reset = 0x3,
.ro = 0x3,
},{ .name = "TRNG_IER", .addr = A_TRNG_IER,
.pre_write = trng_ier_prew,
},{ .name = "TRNG_IDR", .addr = A_TRNG_IDR,
.pre_write = trng_idr_prew,
},{ .name = "SLV_ERR_CTRL", .addr = A_SLV_ERR_CTRL,
}
};
static const MemoryRegionOps trng_ops = {
.read = trng_register_read,
.write = trng_register_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void trng_init(Object *obj)
{
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
RegisterInfoArray *reg_array;
reg_array =
register_init_block32(DEVICE(obj), trng_regs_info,
ARRAY_SIZE(trng_regs_info),
s->regs_info, s->regs,
&trng_ops,
XLNX_VERSAL_TRNG_ERR_DEBUG,
R_MAX * 4);
sysbus_init_mmio(sbd, &reg_array->mem);
sysbus_init_irq(sbd, &s->irq);
s->prng = g_rand_new();
}
static void trng_unrealize(DeviceState *dev)
{
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(dev);
g_rand_free(s->prng);
s->prng = NULL;
}
static void trng_reset_hold(Object *obj)
{
trng_reset(XLNX_VERSAL_TRNG(obj));
}
static void trng_prop_fault_event_set(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
Property *prop = opaque;
uint32_t *events = object_field_prop_ptr(obj, prop);
visit_type_uint32(v, name, events, errp);
if (*errp) {
return;
}
trng_fault_event_set(XLNX_VERSAL_TRNG(obj), *events);
}
static const PropertyInfo trng_prop_fault_events = {
.name = "uint32:bits",
.description = "Set to trigger TRNG fault events",
.set = trng_prop_fault_event_set,
.realized_set_allowed = true,
};
static PropertyInfo trng_prop_uint64; /* to extend qdev_prop_uint64 */
static Property trng_props[] = {
DEFINE_PROP_UINT64("forced-prng", XlnxVersalTRng, forced_prng_seed, 0),
DEFINE_PROP_UINT32("hw-version", XlnxVersalTRng, hw_version, 0x0200),
DEFINE_PROP("fips-fault-events", XlnxVersalTRng, forced_faults,
trng_prop_fault_events, uint32_t),
DEFINE_PROP_END_OF_LIST(),
};
static const VMStateDescription vmstate_trng = {
.name = TYPE_XLNX_VERSAL_TRNG,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(rand_count, XlnxVersalTRng),
VMSTATE_UINT64(rand_reseed, XlnxVersalTRng),
VMSTATE_UINT64(forced_prng_count, XlnxVersalTRng),
VMSTATE_UINT64_ARRAY(tst_seed, XlnxVersalTRng, 2),
VMSTATE_UINT32_ARRAY(regs, XlnxVersalTRng, R_MAX),
VMSTATE_END_OF_LIST(),
}
};
static void trng_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->vmsd = &vmstate_trng;
dc->unrealize = trng_unrealize;
rc->phases.hold = trng_reset_hold;
/* Clone uint64 property with set allowed after realized */
trng_prop_uint64 = qdev_prop_uint64;
trng_prop_uint64.realized_set_allowed = true;
trng_props[0].info = &trng_prop_uint64;
device_class_set_props(dc, trng_props);
}
static const TypeInfo trng_info = {
.name = TYPE_XLNX_VERSAL_TRNG,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(XlnxVersalTRng),
.class_init = trng_class_init,
.instance_init = trng_init,
};
static void trng_register_types(void)
{
type_register_static(&trng_info);
}
type_init(trng_register_types)

6
hw/watchdog/trace-events
View file

@ -17,6 +17,12 @@ cmsdk_apb_watchdog_lock(uint32_t lock) "CMSDK APB watchdog: lock %" PRIu32
aspeed_wdt_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
aspeed_wdt_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
# wdt_imx2.c
imx2_wdt_read(uint32_t addr, uint16_t data) "[0x%" PRIx32 "] -> 0x%" PRIx16
imx2_wdt_write(uint32_t addr, uint16_t data) "[0x%" PRIx32 "] <- 0x%" PRIx16
imx2_wdt_interrupt(void) ""
imx2_wdt_expired(void) ""
# spapr_watchdog.c
spapr_watchdog_start(uint64_t flags, uint64_t num, uint64_t timeout) "Flags 0x%" PRIx64 " num=%" PRId64 " %" PRIu64 "ms"
spapr_watchdog_stop(uint64_t num, uint64_t ret) "num=%" PRIu64 " ret=%" PRId64

28
hw/watchdog/wdt_imx2.c
View file

@ -17,11 +17,14 @@
#include "hw/qdev-properties.h"
#include "hw/watchdog/wdt_imx2.h"
#include "trace.h"
static void imx2_wdt_interrupt(void *opaque)
{
IMX2WdtState *s = IMX2_WDT(opaque);
trace_imx2_wdt_interrupt();
s->wicr |= IMX2_WDT_WICR_WTIS;
qemu_set_irq(s->irq, 1);
}
@ -30,6 +33,8 @@ static void imx2_wdt_expired(void *opaque)
{
IMX2WdtState *s = IMX2_WDT(opaque);
trace_imx2_wdt_expired();
s->wrsr = IMX2_WDT_WRSR_TOUT;
/* Perform watchdog action if watchdog is enabled */
@ -67,20 +72,29 @@ static void imx2_wdt_reset(DeviceState *dev)
static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, unsigned int size)
{
IMX2WdtState *s = IMX2_WDT(opaque);
uint16_t value = 0;
switch (addr) {
case IMX2_WDT_WCR:
return s->wcr;
value = s->wcr;
break;
case IMX2_WDT_WSR:
return s->wsr;
value = s->wsr;
break;
case IMX2_WDT_WRSR:
return s->wrsr;
value = s->wrsr;
break;
case IMX2_WDT_WICR:
return s->wicr;
value = s->wicr;
break;
case IMX2_WDT_WMCR:
return s->wmcr;
value = s->wmcr;
break;
}
return 0;
trace_imx2_wdt_read(addr, value);
return value;
}
static void imx_wdt2_update_itimer(IMX2WdtState *s, bool start)
@ -137,6 +151,8 @@ static void imx2_wdt_write(void *opaque, hwaddr addr,
{
IMX2WdtState *s = IMX2_WDT(opaque);
trace_imx2_wdt_write(addr, value);
switch (addr) {
case IMX2_WDT_WCR:
if (s->wcr_locked) {