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target/riscv: rvv-1.0: find-first-set mask bit instruction

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Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-31-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2021-12-10 15:56:16 +08:00 • committed by Alistair Francis
parent 0014aa741d
commit d71a24fc82
4 changed files with 7 additions and 7 deletions
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4
target/riscv/insn_trans/trans_rvv.c.inc
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@ -2696,7 +2696,7 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)
}
/* vmfirst find-first-set mask bit */
static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
{
if (require_rvv(s) &&
vext_check_isa_ill(s)) {
@ -2715,7 +2715,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc);
gen_set_gpr(s, a->rd, dst);
tcg_temp_free_ptr(mask);