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target/hppa: Use TCG_COND_TST* in do_cond
We can directly test bits of a 32-bit comparison without zero or sign-extending an intermediate result. We can directly test bit 0 for odd/even. Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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1 changed files with 28 additions and 36 deletions
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@ -776,28 +776,36 @@ static bool cond_need_cb(int c)
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static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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TCGv_i64 res, TCGv_i64 uv, TCGv_i64 sv)
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TCGv_i64 res, TCGv_i64 uv, TCGv_i64 sv)
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{
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{
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TCGCond sign_cond, zero_cond;
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uint64_t sign_imm, zero_imm;
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DisasCond cond;
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DisasCond cond;
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TCGv_i64 tmp;
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TCGv_i64 tmp;
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if (d) {
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/* 64-bit condition. */
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sign_imm = 0;
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sign_cond = TCG_COND_LT;
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zero_imm = 0;
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zero_cond = TCG_COND_EQ;
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} else {
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/* 32-bit condition. */
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sign_imm = 1ull << 31;
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sign_cond = TCG_COND_TSTNE;
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zero_imm = UINT32_MAX;
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zero_cond = TCG_COND_TSTEQ;
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}
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switch (cf >> 1) {
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switch (cf >> 1) {
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case 0: /* Never / TR (0 / 1) */
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case 0: /* Never / TR (0 / 1) */
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cond = cond_make_f();
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cond = cond_make_f();
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break;
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break;
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case 1: /* = / <> (Z / !Z) */
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case 1: /* = / <> (Z / !Z) */
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if (!d) {
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cond = cond_make_vi(zero_cond, res, zero_imm);
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tmp = tcg_temp_new_i64();
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tcg_gen_ext32u_i64(tmp, res);
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res = tmp;
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}
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cond = cond_make_vi(TCG_COND_EQ, res, 0);
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break;
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break;
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case 2: /* < / >= (N ^ V / !(N ^ V) */
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case 2: /* < / >= (N ^ V / !(N ^ V) */
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tmp = tcg_temp_new_i64();
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tmp = tcg_temp_new_i64();
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tcg_gen_xor_i64(tmp, res, sv);
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tcg_gen_xor_i64(tmp, res, sv);
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if (!d) {
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cond = cond_make_ti(sign_cond, tmp, sign_imm);
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tcg_gen_ext32s_i64(tmp, tmp);
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}
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cond = cond_make_ti(TCG_COND_LT, tmp, 0);
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break;
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break;
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case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
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case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
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/*
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/*
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@ -805,21 +813,15 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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* (N ^ V) | Z
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* (N ^ V) | Z
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* ((res < 0) ^ (sv < 0)) | !res
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* ((res < 0) ^ (sv < 0)) | !res
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* ((res ^ sv) < 0) | !res
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* ((res ^ sv) < 0) | !res
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* (~(res ^ sv) >= 0) | !res
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* ((res ^ sv) < 0 ? 1 : !res)
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* !(~(res ^ sv) >> 31) | !res
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* !((res ^ sv) < 0 ? 0 : res)
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* !(~(res ^ sv) >> 31 & res)
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*/
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*/
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tmp = tcg_temp_new_i64();
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tmp = tcg_temp_new_i64();
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tcg_gen_eqv_i64(tmp, res, sv);
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tcg_gen_xor_i64(tmp, res, sv);
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if (!d) {
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tcg_gen_movcond_i64(sign_cond, tmp,
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tcg_gen_sextract_i64(tmp, tmp, 31, 1);
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tmp, tcg_constant_i64(sign_imm),
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tcg_gen_and_i64(tmp, tmp, res);
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ctx->zero, res);
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tcg_gen_ext32u_i64(tmp, tmp);
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cond = cond_make_ti(zero_cond, tmp, zero_imm);
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} else {
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tcg_gen_sari_i64(tmp, tmp, 63);
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tcg_gen_and_i64(tmp, tmp, res);
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}
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cond = cond_make_ti(TCG_COND_EQ, tmp, 0);
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break;
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break;
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case 4: /* NUV / UV (!UV / UV) */
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case 4: /* NUV / UV (!UV / UV) */
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cond = cond_make_vi(TCG_COND_EQ, uv, 0);
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cond = cond_make_vi(TCG_COND_EQ, uv, 0);
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@ -827,23 +829,13 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
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case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */
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case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */
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tmp = tcg_temp_new_i64();
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tmp = tcg_temp_new_i64();
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tcg_gen_movcond_i64(TCG_COND_EQ, tmp, uv, ctx->zero, ctx->zero, res);
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tcg_gen_movcond_i64(TCG_COND_EQ, tmp, uv, ctx->zero, ctx->zero, res);
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if (!d) {
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cond = cond_make_ti(zero_cond, tmp, zero_imm);
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tcg_gen_ext32u_i64(tmp, tmp);
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}
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cond = cond_make_ti(TCG_COND_EQ, tmp, 0);
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break;
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break;
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case 6: /* SV / NSV (V / !V) */
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case 6: /* SV / NSV (V / !V) */
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if (!d) {
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cond = cond_make_vi(sign_cond, sv, sign_imm);
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tmp = tcg_temp_new_i64();
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tcg_gen_ext32s_i64(tmp, sv);
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sv = tmp;
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}
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cond = cond_make_ti(TCG_COND_LT, sv, 0);
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break;
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break;
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case 7: /* OD / EV */
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case 7: /* OD / EV */
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tmp = tcg_temp_new_i64();
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cond = cond_make_vi(TCG_COND_TSTNE, res, 1);
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tcg_gen_andi_i64(tmp, res, 1);
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cond = cond_make_ti(TCG_COND_NE, tmp, 0);
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break;
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break;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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