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Hexagon (target/hexagon) implement mutability mask for GPRs

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Some registers are defined to have immutable bits, this commit
will implement that behavior.

Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20230105102349.2181856-1-quic_mliebel@quicinc.com>
This commit is contained in:
Marco Liebel 2023-01-05 02:23:49 -08:00 • committed by Taylor Simpson
parent 8a9ce0952b
commit d63aeb3b7e
3 changed files with 195 additions and 2 deletions
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44
target/hexagon/genptr.c
View file

@ -43,6 +43,33 @@ TCGv gen_read_preg(TCGv pred, uint8_t num)
return pred;
}
#define IMMUTABLE (~0)
static const target_ulong reg_immut_masks[TOTAL_PER_THREAD_REGS] = {
[HEX_REG_USR] = 0xc13000c0,
[HEX_REG_PC] = IMMUTABLE,
[HEX_REG_GP] = 0x3f,
[HEX_REG_UPCYCLELO] = IMMUTABLE,
[HEX_REG_UPCYCLEHI] = IMMUTABLE,
[HEX_REG_UTIMERLO] = IMMUTABLE,
[HEX_REG_UTIMERHI] = IMMUTABLE,
};
static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val,
target_ulong reg_mask)
{
if (reg_mask) {
TCGv tmp = tcg_temp_new();
/* new_val = (new_val & ~reg_mask) | (cur_val & reg_mask) */
tcg_gen_andi_tl(new_val, new_val, ~reg_mask);
tcg_gen_andi_tl(tmp, cur_val, reg_mask);
tcg_gen_or_tl(new_val, new_val, tmp);
tcg_temp_free(tmp);
}
}
static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
uint32_t slot)
{
@ -69,6 +96,9 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
void gen_log_reg_write(int rnum, TCGv val)
{
const target_ulong reg_mask = reg_immut_masks[rnum];
gen_masked_reg_write(val, hex_gpr[rnum], reg_mask);
tcg_gen_mov_tl(hex_new_value[rnum], val);
if (HEX_DEBUG) {
/* Do this so HELPER(debug_commit_end) will know */
@ -114,19 +144,29 @@ static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,
static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
{
const target_ulong reg_mask_low = reg_immut_masks[rnum];
const target_ulong reg_mask_high = reg_immut_masks[rnum + 1];
TCGv val32 = tcg_temp_new();
/* Low word */
tcg_gen_extrl_i64_i32(hex_new_value[rnum], val);
tcg_gen_extrl_i64_i32(val32, val);
gen_masked_reg_write(val32, hex_gpr[rnum], reg_mask_low);
tcg_gen_mov_tl(hex_new_value[rnum], val32);
if (HEX_DEBUG) {
/* Do this so HELPER(debug_commit_end) will know */
tcg_gen_movi_tl(hex_reg_written[rnum], 1);
}
/* High word */
tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val);
tcg_gen_extrh_i64_i32(val32, val);
gen_masked_reg_write(val32, hex_gpr[rnum + 1], reg_mask_high);
tcg_gen_mov_tl(hex_new_value[rnum + 1], val32);
if (HEX_DEBUG) {
/* Do this so HELPER(debug_commit_end) will know */
tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
}
tcg_temp_free(val32);
}
void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)