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Make PowerPC cache line size implementation dependant.

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Implement dcbz tunable cache line size for PowerPC 970.
Make hardware reset vector implementation dependant.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3321 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-10-04 00:51:58 +00:00
parent 064034211a
commit d63001d114
7 changed files with 620 additions and 60 deletions
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12
target-ppc/op_helper.c
View file

@ -1061,21 +1061,21 @@ void do_POWER_clcs (void)
switch (T0) {
case 0x0CUL:
/* Instruction cache line size */
T0 = ICACHE_LINE_SIZE;
T0 = env->icache_line_size;
break;
case 0x0DUL:
/* Data cache line size */
T0 = DCACHE_LINE_SIZE;
T0 = env->dcache_line_size;
break;
case 0x0EUL:
/* Minimum cache line size */
T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
T0 = env->icache_line_size < env->dcache_line_size ?
env->icache_line_size : env->dcache_line_size;
break;
case 0x0FUL:
/* Maximum cache line size */
T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
T0 = env->icache_line_size > env->dcache_line_size ?
env->icache_line_size : env->dcache_line_size;
break;
default:
/* Undefined */