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virtio,pc,pci: features, cleanups, fixes

Browse source 
mostly vhost-vdpa:
     guest announce feature emulation when using shadow virtqueue
     support for configure interrupt
     startup speed ups
 
 an acpi change to only generate cluster node in PPTT when specified for arm
 
 misc fixes, cleanups
 
 Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging

virtio,pc,pci: features, cleanups, fixes

mostly vhost-vdpa:
    guest announce feature emulation when using shadow virtqueue
    support for configure interrupt
    startup speed ups

an acpi change to only generate cluster node in PPTT when specified for arm

misc fixes, cleanups

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Sun 08 Jan 2023 08:01:39 GMT
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (50 commits)
  vhost-scsi: fix memleak of vsc->inflight
  acpi: cpuhp: fix guest-visible maximum access size to the legacy reg block
  tests: acpi: aarch64: Add *.topology tables
  tests: acpi: aarch64: Add topology test for aarch64
  tests: acpi: Add and whitelist *.topology blobs
  tests: virt: Update expected ACPI tables for virt test
  hw/acpi/aml-build: Only generate cluster node in PPTT when specified
  tests: virt: Allow changes to PPTT test table
  virtio-pci: fix proxy->vector_irqfd leak in virtio_pci_set_guest_notifiers
  vdpa: commit all host notifier MRs in a single MR transaction
  vhost: configure all host notifiers in a single MR transaction
  vhost: simplify vhost_dev_enable_notifiers
  vdpa: harden the error path if get_iova_range failed
  vdpa-dev: get iova range explicitly
  docs/devel: Rules on #include in headers
  include: Include headers where needed
  include/hw/virtio: Break inclusion loop
  include/hw/cxl: Break inclusion loop cxl_pci.h and cxl_cdat_h
  include/hw/pci: Include hw/pci/pci.h where needed
  include/hw/pci: Split pci_device.h off pci.h
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-01-09 10:07:11 +00:00
commit d6271b6572
205 changed files with 1416 additions and 827 deletions
Download patch file Download diff file Expand all files Collapse all files

3
include/hw/acpi/erst.h
View file

@ -11,6 +11,9 @@
#ifndef HW_ACPI_ERST_H
#define HW_ACPI_ERST_H
#include "hw/acpi/bios-linker-loader.h"
#include "qom/object.h"
void build_erst(GArray *table_data, BIOSLinker *linker, Object *erst_dev,
const char *oem_id, const char *oem_table_id);

2
include/hw/acpi/piix4.h
View file

@ -22,7 +22,7 @@
#ifndef HW_ACPI_PIIX4_H
#define HW_ACPI_PIIX4_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/cpu_hotplug.h"
#include "hw/acpi/memory_hotplug.h"

1
include/hw/arm/allwinner-a10.h
View file

@ -4,6 +4,7 @@
#include "qemu/error-report.h"
#include "hw/char/serial.h"
#include "hw/arm/boot.h"
#include "hw/pci/pci_device.h"
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/intc/allwinner-a10-pic.h"
#include "hw/net/allwinner_emac.h"

3
include/hw/boards.h
View file

@ -129,11 +129,14 @@ typedef struct {
* @prefer_sockets - whether sockets are preferred over cores in smp parsing
* @dies_supported - whether dies are supported by the machine
* @clusters_supported - whether clusters are supported by the machine
* @has_clusters - whether clusters are explicitly specified in the user
* provided SMP configuration
*/
typedef struct {
bool prefer_sockets;
bool dies_supported;
bool clusters_supported;
bool has_clusters;
} SMPCompatProps;
/**

1
include/hw/char/cmsdk-apb-uart.h
View file

@ -15,6 +15,7 @@
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qapi/error.h"
#include "qom/object.h"
#define TYPE_CMSDK_APB_UART "cmsdk-apb-uart"

1
include/hw/char/goldfish_tty.h
View file

@ -12,6 +12,7 @@
#include "qemu/fifo8.h"
#include "chardev/char-fe.h"
#include "hw/sysbus.h"
#define TYPE_GOLDFISH_TTY "goldfish_tty"
OBJECT_DECLARE_SIMPLE_TYPE(GoldfishTTYState, GOLDFISH_TTY)

1
include/hw/char/xilinx_uartlite.h
View file

@ -17,6 +17,7 @@
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
qemu_irq irq,

1
include/hw/cris/etraxfs.h
View file

@ -29,6 +29,7 @@
#include "hw/cris/etraxfs_dma.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
DeviceState *etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr,
struct etraxfs_dma_client *dma_out,

5
include/hw/cxl/cxl.h
View file

@ -13,7 +13,6 @@
#include "qapi/qapi-types-machine.h"
#include "qapi/qapi-visit-machine.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_host.h"
#include "cxl_pci.h"
#include "cxl_component.h"
@ -24,10 +23,12 @@
#define CXL_WINDOW_MAX 10
typedef struct PXBDev PXBDev;
typedef struct CXLFixedWindow {
uint64_t size;
char **targets;
struct PXBDev *target_hbs[8];
PXBDev *target_hbs[8];
uint8_t num_targets;
uint8_t enc_int_ways;
uint8_t enc_int_gran;

1
include/hw/cxl/cxl_cdat.h
View file

@ -11,6 +11,7 @@
#define CXL_CDAT_H
#include "hw/cxl/cxl_pci.h"
#include "hw/pci/pcie_doe.h"
/*
* Reference:

1
include/hw/cxl/cxl_component.h
View file

@ -18,6 +18,7 @@
#include "qemu/compiler.h"
#include "qemu/range.h"
#include "qemu/typedefs.h"
#include "hw/cxl/cxl_cdat.h"
#include "hw/register.h"
#include "qapi/error.h"

2
include/hw/cxl/cxl_device.h
View file

@ -10,6 +10,8 @@
#ifndef CXL_DEVICE_H
#define CXL_DEVICE_H
#include "hw/cxl/cxl_component.h"
#include "hw/pci/pci_device.h"
#include "hw/register.h"
/*

3
include/hw/cxl/cxl_pci.h
View file

@ -11,9 +11,6 @@
#define CXL_PCI_H
#include "qemu/compiler.h"
#include "hw/pci/pci.h"
#include "hw/pci/pcie.h"
#include "hw/cxl/cxl_cdat.h"
#define CXL_VENDOR_ID 0x1e98

3
include/hw/display/macfb.h
View file

@ -15,9 +15,10 @@
#include "exec/memory.h"
#include "hw/irq.h"
#include "hw/nubus/nubus.h"
#include "hw/sysbus.h"
#include "ui/console.h"
#include "qemu/timer.h"
#include "qom/object.h"
typedef enum {
MACFB_DISPLAY_APPLE_21_COLOR = 0,

2
include/hw/dma/sifive_pdma.h
View file

@ -23,6 +23,8 @@
#ifndef SIFIVE_PDMA_H
#define SIFIVE_PDMA_H
#include "hw/sysbus.h"
struct sifive_pdma_chan {
uint32_t control;
uint32_t next_config;

4
include/hw/i386/ich9.h
View file

@ -5,12 +5,8 @@
#include "hw/sysbus.h"
#include "hw/i386/pc.h"
#include "hw/isa/apm.h"
#include "hw/pci/pci.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci_bridge.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
#include "hw/pci/pci_bus.h"
#include "qom/object.h"
void ich9_lpc_set_irq(void *opaque, int irq_num, int level);

1
include/hw/i386/ioapic_internal.h
View file

@ -23,6 +23,7 @@
#define QEMU_IOAPIC_INTERNAL_H
#include "exec/memory.h"
#include "hw/i386/ioapic.h"
#include "hw/sysbus.h"
#include "qemu/notify.h"
#include "qom/object.h"

1
include/hw/i386/sgx-epc.h
View file

@ -12,6 +12,7 @@
#ifndef QEMU_SGX_EPC_H
#define QEMU_SGX_EPC_H
#include "hw/qdev-core.h"
#include "hw/i386/hostmem-epc.h"
#define TYPE_SGX_EPC "sgx-epc"

1
include/hw/i386/x86-iommu.h
View file

@ -21,7 +21,6 @@
#define HW_I386_X86_IOMMU_H
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
#include "hw/pci/msi.h"
#include "qom/object.h"

2
include/hw/ide/pci.h
View file

@ -2,7 +2,7 @@
#define HW_IDE_PCI_H
#include "hw/ide/internal.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "qom/object.h"
#define BM_STATUS_DMAING 0x01

2
include/hw/intc/goldfish_pic.h
View file

@ -10,6 +10,8 @@
#ifndef HW_INTC_GOLDFISH_PIC_H
#define HW_INTC_GOLDFISH_PIC_H
#include "hw/sysbus.h"
#define TYPE_GOLDFISH_PIC "goldfish_pic"
OBJECT_DECLARE_SIMPLE_TYPE(GoldfishPICState, GOLDFISH_PIC)

2
include/hw/intc/loongarch_pch_msi.h
View file

@ -5,6 +5,8 @@
* Copyright (C) 2021 Loongson Technology Corporation Limited
*/
#include "hw/sysbus.h"
#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)

2
include/hw/intc/loongarch_pch_pic.h
View file

@ -5,6 +5,8 @@
* Copyright (c) 2021 Loongson Technology Corporation Limited
*/
#include "hw/sysbus.h"
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)

2
include/hw/intc/nios2_vic.h
View file

@ -35,6 +35,8 @@
#ifndef HW_INTC_NIOS2_VIC_H
#define HW_INTC_NIOS2_VIC_H
#include "hw/sysbus.h"
#define TYPE_NIOS2_VIC "nios2-vic"
OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC)

1
include/hw/isa/vt82c686.h
View file

@ -1,7 +1,6 @@
#ifndef HW_VT82C686_H
#define HW_VT82C686_H
#include "hw/pci/pci.h"
#define TYPE_VT82C686B_ISA "vt82c686b-isa"
#define TYPE_VT82C686B_USB_UHCI "vt82c686b-usb-uhci"

2
include/hw/misc/macio/macio.h
View file

@ -27,7 +27,7 @@
#define MACIO_H
#include "hw/char/escc.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/ide/internal.h"
#include "hw/intc/heathrow_pic.h"
#include "hw/misc/macio/cuda.h"

2
include/hw/misc/mchp_pfsoc_dmc.h
View file

@ -23,6 +23,8 @@
#ifndef MCHP_PFSOC_DMC_H
#define MCHP_PFSOC_DMC_H
#include "hw/sysbus.h"
/* DDR SGMII PHY module */
#define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE 0x1000

2
include/hw/misc/mchp_pfsoc_ioscb.h
View file

@ -23,6 +23,8 @@
#ifndef MCHP_PFSOC_IOSCB_H
#define MCHP_PFSOC_IOSCB_H
#include "hw/sysbus.h"
typedef struct MchpPfSoCIoscbState {
SysBusDevice parent;
MemoryRegion container;

2
include/hw/misc/mchp_pfsoc_sysreg.h
View file

@ -23,6 +23,8 @@
#ifndef MCHP_PFSOC_SYSREG_H
#define MCHP_PFSOC_SYSREG_H
#include "hw/sysbus.h"
#define MCHP_PFSOC_SYSREG_REG_SIZE 0x2000
typedef struct MchpPfSoCSysregState {

1
include/hw/misc/pvpanic.h
View file

@ -15,6 +15,7 @@
#ifndef HW_MISC_PVPANIC_H
#define HW_MISC_PVPANIC_H
#include "exec/memory.h"
#include "qom/object.h"
#define TYPE_PVPANIC_ISA_DEVICE "pvpanic"

3
include/hw/misc/sifive_e_prci.h
View file

@ -18,7 +18,8 @@
#ifndef HW_SIFIVE_E_PRCI_H
#define HW_SIFIVE_E_PRCI_H
#include "qom/object.h"
#include "hw/sysbus.h"
enum {
SIFIVE_E_PRCI_HFROSCCFG = 0x0,

3
include/hw/misc/sifive_u_otp.h
View file

@ -18,7 +18,8 @@
#ifndef HW_SIFIVE_U_OTP_H
#define HW_SIFIVE_U_OTP_H
#include "qom/object.h"
#include "hw/sysbus.h"
#define SIFIVE_U_OTP_PA 0x00
#define SIFIVE_U_OTP_PAIO 0x04

3
include/hw/misc/sifive_u_prci.h
View file

@ -18,7 +18,8 @@
#ifndef HW_SIFIVE_U_PRCI_H
#define HW_SIFIVE_U_PRCI_H
#include "qom/object.h"
#include "hw/sysbus.h"
#define SIFIVE_U_PRCI_HFXOSCCFG 0x00
#define SIFIVE_U_PRCI_COREPLLCFG0 0x04

2
include/hw/misc/virt_ctrl.h
View file

@ -7,6 +7,8 @@
#ifndef VIRT_CTRL_H
#define VIRT_CTRL_H
#include "hw/sysbus.h"
#define TYPE_VIRT_CTRL "virt-ctrl"
OBJECT_DECLARE_SIMPLE_TYPE(VirtCtrlState, VIRT_CTRL)

1
include/hw/misc/xlnx-versal-pmc-iou-slcr.h
View file

@ -54,6 +54,7 @@
#ifndef XLNX_VERSAL_PMC_IOU_SLCR_H
#define XLNX_VERSAL_PMC_IOU_SLCR_H
#include "hw/sysbus.h"
#include "hw/register.h"
#define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr"

2
include/hw/net/lasi_82596.h
View file

@ -10,7 +10,7 @@
#include "net/net.h"
#include "hw/net/i82596.h"
#include "qom/object.h"
#include "hw/sysbus.h"
#define TYPE_LASI_82596 "lasi_82596"
typedef struct SysBusI82596State SysBusI82596State;

1
include/hw/net/xlnx-zynqmp-can.h
View file

@ -30,6 +30,7 @@
#ifndef XLNX_ZYNQMP_CAN_H
#define XLNX_ZYNQMP_CAN_H
#include "hw/sysbus.h"
#include "hw/register.h"
#include "net/can_emu.h"
#include "net/can_host.h"

3
include/hw/pci-host/designware.h
View file

@ -22,9 +22,6 @@
#define DESIGNWARE_H
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci_bridge.h"
#include "qom/object.h"

2
include/hw/pci-host/gpex.h
View file

@ -22,7 +22,7 @@
#include "exec/hwaddr.h"
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pcie_host.h"
#include "qom/object.h"

2
include/hw/pci-host/i440fx.h
View file

@ -11,7 +11,7 @@
#ifndef HW_PCI_I440FX_H
#define HW_PCI_I440FX_H
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_device.h"
#include "hw/pci-host/pam.h"
#include "qom/object.h"

2
include/hw/pci-host/ls7a.h
View file

@ -8,8 +8,6 @@
#ifndef HW_LS7A_H
#define HW_LS7A_H
#include "hw/pci/pci.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci-host/pam.h"
#include "qemu/units.h"
#include "qemu/range.h"

2
include/hw/pci-host/pnv_phb3.h
View file

@ -10,8 +10,6 @@
#ifndef PCI_HOST_PNV_PHB3_H
#define PCI_HOST_PNV_PHB3_H
#include "hw/pci/pcie_host.h"
#include "hw/pci/pcie_port.h"
#include "hw/ppc/xics.h"
#include "qom/object.h"
#include "hw/pci-host/pnv_phb.h"

3
include/hw/pci-host/pnv_phb4.h
View file

@ -10,8 +10,7 @@
#ifndef PCI_HOST_PNV_PHB4_H
#define PCI_HOST_PNV_PHB4_H
#include "hw/pci/pcie_host.h"
#include "hw/pci/pcie_port.h"
#include "hw/pci/pci_bus.h"
#include "hw/ppc/xive.h"
#include "qom/object.h"

2
include/hw/pci-host/q35.h
View file

@ -22,7 +22,7 @@
#ifndef HW_Q35_H
#define HW_Q35_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci-host/pam.h"
#include "qemu/units.h"

2
include/hw/pci-host/sabre.h
View file

@ -1,7 +1,7 @@
#ifndef HW_PCI_HOST_SABRE_H
#define HW_PCI_HOST_SABRE_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_host.h"
#include "hw/sparc/sun4u_iommu.h"
#include "qom/object.h"

1
include/hw/pci-host/xilinx-pcie.h
View file

@ -21,7 +21,6 @@
#define HW_XILINX_PCIE_H
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pcie_host.h"
#include "qom/object.h"

2
include/hw/pci/msi.h
View file

@ -21,7 +21,7 @@
#ifndef QEMU_MSI_H
#define QEMU_MSI_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
struct MSIMessage {
uint64_t address;

341
include/hw/pci/pci.h
View file

@ -166,7 +166,6 @@ enum {
#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
#include "hw/pci/pci_regs.h"
#include "hw/pci/pcie.h"
/* PCI HEADER_TYPE */
#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
@ -210,23 +209,6 @@ enum {
QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR),
};
#define TYPE_PCI_DEVICE "pci-device"
typedef struct PCIDeviceClass PCIDeviceClass;
DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
PCI_DEVICE, TYPE_PCI_DEVICE)
/*
* Implemented by devices that can be plugged on CXL buses. In the spec, this is
* actually a "CXL Component, but we name it device to match the PCI naming.
*/
#define INTERFACE_CXL_DEVICE "cxl-device"
/* Implemented by devices that can be plugged on PCI Express buses */
#define INTERFACE_PCIE_DEVICE "pci-express-device"
/* Implemented by devices that can be plugged on Conventional PCI buses */
#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
typedef struct PCIINTxRoute {
enum {
PCI_INTX_ENABLED,
@ -236,24 +218,6 @@ typedef struct PCIINTxRoute {
int irq;
} PCIINTxRoute;
struct PCIDeviceClass {
DeviceClass parent_class;
void (*realize)(PCIDevice *dev, Error **errp);
PCIUnregisterFunc *exit;
PCIConfigReadFunc *config_read;
PCIConfigWriteFunc *config_write;
uint16_t vendor_id;
uint16_t device_id;
uint8_t revision;
uint16_t class_id;
uint16_t subsystem_vendor_id; /* only for header type = 0 */
uint16_t subsystem_id; /* only for header type = 0 */
const char *romfile; /* rom bar */
};
typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
MSIMessage msg);
@ -262,126 +226,6 @@ typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
unsigned int vector_start,
unsigned int vector_end);
enum PCIReqIDType {
PCI_REQ_ID_INVALID = 0,
PCI_REQ_ID_BDF,
PCI_REQ_ID_SECONDARY_BUS,
PCI_REQ_ID_MAX,
};
typedef enum PCIReqIDType PCIReqIDType;
struct PCIReqIDCache {
PCIDevice *dev;
PCIReqIDType type;
};
typedef struct PCIReqIDCache PCIReqIDCache;
struct PCIDevice {
DeviceState qdev;
bool partially_hotplugged;
bool has_power;
/* PCI config space */
uint8_t *config;
/* Used to enable config checks on load. Note that writable bits are
* never checked even if set in cmask. */
uint8_t *cmask;
/* Used to implement R/W bytes */
uint8_t *wmask;
/* Used to implement RW1C(Write 1 to Clear) bytes */
uint8_t *w1cmask;
/* Used to allocate config space for capabilities. */
uint8_t *used;
/* the following fields are read only */
int32_t devfn;
/* Cached device to fetch requester ID from, to avoid the PCI
* tree walking every time we invoke PCI request (e.g.,
* MSI). For conventional PCI root complex, this field is
* meaningless. */
PCIReqIDCache requester_id_cache;
char name[64];
PCIIORegion io_regions[PCI_NUM_REGIONS];
AddressSpace bus_master_as;
MemoryRegion bus_master_container_region;
MemoryRegion bus_master_enable_region;
/* do not access the following fields */
PCIConfigReadFunc *config_read;
PCIConfigWriteFunc *config_write;
/* Legacy PCI VGA regions */
MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
bool has_vga;
/* Current IRQ levels. Used internally by the generic PCI code. */
uint8_t irq_state;
/* Capability bits */
uint32_t cap_present;
/* Offset of MSI-X capability in config space */
uint8_t msix_cap;
/* MSI-X entries */
int msix_entries_nr;
/* Space to store MSIX table & pending bit array */
uint8_t *msix_table;
uint8_t *msix_pba;
/* May be used by INTx or MSI during interrupt notification */
void *irq_opaque;
MSITriggerFunc *msi_trigger;
MSIPrepareMessageFunc *msi_prepare_message;
MSIxPrepareMessageFunc *msix_prepare_message;
/* MemoryRegion container for msix exclusive BAR setup */
MemoryRegion msix_exclusive_bar;
/* Memory Regions for MSIX table and pending bit entries. */
MemoryRegion msix_table_mmio;
MemoryRegion msix_pba_mmio;
/* Reference-count for entries actually in use by driver. */
unsigned *msix_entry_used;
/* MSIX function mask set or MSIX disabled */
bool msix_function_masked;
/* Version id needed for VMState */
int32_t version_id;
/* Offset of MSI capability in config space */
uint8_t msi_cap;
/* PCI Express */
PCIExpressDevice exp;
/* SHPC */
SHPCDevice *shpc;
/* Location of option rom */
char *romfile;
uint32_t romsize;
bool has_rom;
MemoryRegion rom;
uint32_t rom_bar;
/* INTx routing notifier */
PCIINTxRoutingNotifier intx_routing_notifier;
/* MSI-X notifiers */
MSIVectorUseNotifier msix_vector_use_notifier;
MSIVectorReleaseNotifier msix_vector_release_notifier;
MSIVectorPollNotifier msix_vector_poll_notifier;
/* ID of standby device in net_failover pair */
char *failover_pair_id;
uint32_t acpi_index;
};
void pci_register_bar(PCIDevice *pci_dev, int region_num,
uint8_t attr, MemoryRegion *memory);
void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
@ -742,11 +586,6 @@ void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
void pci_set_irq(PCIDevice *pci_dev, int level);
static inline int pci_intx(PCIDevice *pci_dev)
{
return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
}
static inline void pci_irq_assert(PCIDevice *pci_dev)
{
pci_set_irq(pci_dev, 1);
@ -767,186 +606,6 @@ static inline void pci_irq_pulse(PCIDevice *pci_dev)
pci_irq_deassert(pci_dev);
}
static inline int pci_is_cxl(const PCIDevice *d)
{
return d->cap_present & QEMU_PCIE_CAP_CXL;
}
static inline int pci_is_express(const PCIDevice *d)
{
return d->cap_present & QEMU_PCI_CAP_EXPRESS;
}
static inline int pci_is_express_downstream_port(const PCIDevice *d)
{
uint8_t type;
if (!pci_is_express(d) || !d->exp.exp_cap) {
return 0;
}
type = pcie_cap_get_type(d);
return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
}
static inline int pci_is_vf(const PCIDevice *d)
{
return d->exp.sriov_vf.pf != NULL;
}
static inline uint32_t pci_config_size(const PCIDevice *d)
{
return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
}
static inline uint16_t pci_get_bdf(PCIDevice *dev)
{
return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
}
uint16_t pci_requester_id(PCIDevice *dev);
/* DMA access functions */
static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
{
return &dev->bus_master_as;
}
/**
* pci_dma_rw: Read from or write to an address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault).
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: the number of bytes to read or write
* @dir: indicates the transfer direction
*/
static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len,
DMADirection dir, MemTxAttrs attrs)
{
return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
dir, attrs);
}
/**
* pci_dma_read: Read from an address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault). Called within RCU critical section.
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: length of the data transferred
*/
static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len)
{
return pci_dma_rw(dev, addr, buf, len,
DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
}
/**
* pci_dma_write: Write to address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault).
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: the number of bytes to write
*/
static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
const void *buf, dma_addr_t len)
{
return pci_dma_rw(dev, addr, (void *) buf, len,
DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
}
#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
dma_addr_t addr, \
uint##_bits##_t *val, \
MemTxAttrs attrs) \
{ \
return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
} \
static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
dma_addr_t addr, \
uint##_bits##_t val, \
MemTxAttrs attrs) \
{ \
return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
}
PCI_DMA_DEFINE_LDST(ub, b, 8);
PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
#undef PCI_DMA_DEFINE_LDST
/**
* pci_dma_map: Map device PCI address space range into host virtual address
* @dev: #PCIDevice to be accessed
* @addr: address within that device's address space
* @plen: pointer to length of buffer; updated on return to indicate
* if only a subset of the requested range has been mapped
* @dir: indicates the transfer direction
*
* Return: A host pointer, or %NULL if the resources needed to
* perform the mapping are exhausted (in that case *@plen
* is set to zero).
*/
static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
dma_addr_t *plen, DMADirection dir)
{
return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
MEMTXATTRS_UNSPECIFIED);
}
static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
DMADirection dir, dma_addr_t access_len)
{
dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
}
static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
int alloc_hint)
{
qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
}
extern const VMStateDescription vmstate_pci_device;
#define VMSTATE_PCI_DEVICE(_field, _state) { \
.name = (stringify(_field)), \
.size = sizeof(PCIDevice), \
.vmsd = &vmstate_pci_device, \
.flags = VMS_STRUCT, \
.offset = vmstate_offset_value(_state, _field, PCIDevice), \
}
#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
.name = (stringify(_field)), \
.size = sizeof(PCIDevice), \
.vmsd = &vmstate_pci_device, \
.flags = VMS_STRUCT|VMS_POINTER, \
.offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
}
MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
void pci_set_power(PCIDevice *pci_dev, bool state);

3
include/hw/pci/pci_bridge.h
View file

@ -26,7 +26,7 @@
#ifndef QEMU_PCI_BRIDGE_H
#define QEMU_PCI_BRIDGE_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_bus.h"
#include "hw/cxl/cxl.h"
#include "qom/object.h"
@ -97,7 +97,6 @@ struct PXBDev {
} cxl;
};
typedef struct PXBDev PXBDev;
#define TYPE_PXB_CXL_DEVICE "pxb-cxl"
DECLARE_INSTANCE_CHECKER(PXBDev, PXB_CXL_DEV,
TYPE_PXB_CXL_DEVICE)

350
include/hw/pci/pci_device.h Normal file
View file

@ -0,0 +1,350 @@
#ifndef QEMU_PCI_DEVICE_H
#define QEMU_PCI_DEVICE_H
#include "hw/pci/pci.h"
#include "hw/pci/pcie.h"
#define TYPE_PCI_DEVICE "pci-device"
typedef struct PCIDeviceClass PCIDeviceClass;
DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
PCI_DEVICE, TYPE_PCI_DEVICE)
/*
* Implemented by devices that can be plugged on CXL buses. In the spec, this is
* actually a "CXL Component, but we name it device to match the PCI naming.
*/
#define INTERFACE_CXL_DEVICE "cxl-device"
/* Implemented by devices that can be plugged on PCI Express buses */
#define INTERFACE_PCIE_DEVICE "pci-express-device"
/* Implemented by devices that can be plugged on Conventional PCI buses */
#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
struct PCIDeviceClass {
DeviceClass parent_class;
void (*realize)(PCIDevice *dev, Error **errp);
PCIUnregisterFunc *exit;
PCIConfigReadFunc *config_read;
PCIConfigWriteFunc *config_write;
uint16_t vendor_id;
uint16_t device_id;
uint8_t revision;
uint16_t class_id;
uint16_t subsystem_vendor_id; /* only for header type = 0 */
uint16_t subsystem_id; /* only for header type = 0 */
const char *romfile; /* rom bar */
};
enum PCIReqIDType {
PCI_REQ_ID_INVALID = 0,
PCI_REQ_ID_BDF,
PCI_REQ_ID_SECONDARY_BUS,
PCI_REQ_ID_MAX,
};
typedef enum PCIReqIDType PCIReqIDType;
struct PCIReqIDCache {
PCIDevice *dev;
PCIReqIDType type;
};
typedef struct PCIReqIDCache PCIReqIDCache;
struct PCIDevice {
DeviceState qdev;
bool partially_hotplugged;
bool has_power;
/* PCI config space */
uint8_t *config;
/*
* Used to enable config checks on load. Note that writable bits are
* never checked even if set in cmask.
*/
uint8_t *cmask;
/* Used to implement R/W bytes */
uint8_t *wmask;
/* Used to implement RW1C(Write 1 to Clear) bytes */
uint8_t *w1cmask;
/* Used to allocate config space for capabilities. */
uint8_t *used;
/* the following fields are read only */
int32_t devfn;
/*
* Cached device to fetch requester ID from, to avoid the PCI tree
* walking every time we invoke PCI request (e.g., MSI). For
* conventional PCI root complex, this field is meaningless.
*/
PCIReqIDCache requester_id_cache;
char name[64];
PCIIORegion io_regions[PCI_NUM_REGIONS];
AddressSpace bus_master_as;
MemoryRegion bus_master_container_region;
MemoryRegion bus_master_enable_region;
/* do not access the following fields */
PCIConfigReadFunc *config_read;
PCIConfigWriteFunc *config_write;
/* Legacy PCI VGA regions */
MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
bool has_vga;
/* Current IRQ levels. Used internally by the generic PCI code. */
uint8_t irq_state;
/* Capability bits */
uint32_t cap_present;
/* Offset of MSI-X capability in config space */
uint8_t msix_cap;
/* MSI-X entries */
int msix_entries_nr;
/* Space to store MSIX table & pending bit array */
uint8_t *msix_table;
uint8_t *msix_pba;
/* May be used by INTx or MSI during interrupt notification */
void *irq_opaque;
MSITriggerFunc *msi_trigger;
MSIPrepareMessageFunc *msi_prepare_message;
MSIxPrepareMessageFunc *msix_prepare_message;
/* MemoryRegion container for msix exclusive BAR setup */
MemoryRegion msix_exclusive_bar;
/* Memory Regions for MSIX table and pending bit entries. */
MemoryRegion msix_table_mmio;
MemoryRegion msix_pba_mmio;
/* Reference-count for entries actually in use by driver. */
unsigned *msix_entry_used;
/* MSIX function mask set or MSIX disabled */
bool msix_function_masked;
/* Version id needed for VMState */
int32_t version_id;
/* Offset of MSI capability in config space */
uint8_t msi_cap;
/* PCI Express */
PCIExpressDevice exp;
/* SHPC */
SHPCDevice *shpc;
/* Location of option rom */
char *romfile;
uint32_t romsize;
bool has_rom;
MemoryRegion rom;
uint32_t rom_bar;
/* INTx routing notifier */
PCIINTxRoutingNotifier intx_routing_notifier;
/* MSI-X notifiers */
MSIVectorUseNotifier msix_vector_use_notifier;
MSIVectorReleaseNotifier msix_vector_release_notifier;
MSIVectorPollNotifier msix_vector_poll_notifier;
/* ID of standby device in net_failover pair */
char *failover_pair_id;
uint32_t acpi_index;
};
static inline int pci_intx(PCIDevice *pci_dev)
{
return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
}
static inline int pci_is_cxl(const PCIDevice *d)
{
return d->cap_present & QEMU_PCIE_CAP_CXL;
}
static inline int pci_is_express(const PCIDevice *d)
{
return d->cap_present & QEMU_PCI_CAP_EXPRESS;
}
static inline int pci_is_express_downstream_port(const PCIDevice *d)
{
uint8_t type;
if (!pci_is_express(d) || !d->exp.exp_cap) {
return 0;
}
type = pcie_cap_get_type(d);
return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
}
static inline int pci_is_vf(const PCIDevice *d)
{
return d->exp.sriov_vf.pf != NULL;
}
static inline uint32_t pci_config_size(const PCIDevice *d)
{
return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
}
static inline uint16_t pci_get_bdf(PCIDevice *dev)
{
return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
}
uint16_t pci_requester_id(PCIDevice *dev);
/* DMA access functions */
static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
{
return &dev->bus_master_as;
}
/**
* pci_dma_rw: Read from or write to an address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault).
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: the number of bytes to read or write
* @dir: indicates the transfer direction
*/
static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len,
DMADirection dir, MemTxAttrs attrs)
{
return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
dir, attrs);
}
/**
* pci_dma_read: Read from an address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault). Called within RCU critical section.
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: length of the data transferred
*/
static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len)
{
return pci_dma_rw(dev, addr, buf, len,
DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
}
/**
* pci_dma_write: Write to address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault).
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: the number of bytes to write
*/
static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
const void *buf, dma_addr_t len)
{
return pci_dma_rw(dev, addr, (void *) buf, len,
DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
}
#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
dma_addr_t addr, \
uint##_bits##_t *val, \
MemTxAttrs attrs) \
{ \
return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
} \
static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
dma_addr_t addr, \
uint##_bits##_t val, \
MemTxAttrs attrs) \
{ \
return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
}
PCI_DMA_DEFINE_LDST(ub, b, 8);
PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
#undef PCI_DMA_DEFINE_LDST
/**
* pci_dma_map: Map device PCI address space range into host virtual address
* @dev: #PCIDevice to be accessed
* @addr: address within that device's address space
* @plen: pointer to length of buffer; updated on return to indicate
* if only a subset of the requested range has been mapped
* @dir: indicates the transfer direction
*
* Return: A host pointer, or %NULL if the resources needed to
* perform the mapping are exhausted (in that case *@plen
* is set to zero).
*/
static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
dma_addr_t *plen, DMADirection dir)
{
return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
MEMTXATTRS_UNSPECIFIED);
}
static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
DMADirection dir, dma_addr_t access_len)
{
dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
}
static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
int alloc_hint)
{
qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
}
extern const VMStateDescription vmstate_pci_device;
#define VMSTATE_PCI_DEVICE(_field, _state) { \
.name = (stringify(_field)), \
.size = sizeof(PCIDevice), \
.vmsd = &vmstate_pci_device, \
.flags = VMS_STRUCT, \
.offset = vmstate_offset_value(_state, _field, PCIDevice), \
}
#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
.name = (stringify(_field)), \
.size = sizeof(PCIDevice), \
.vmsd = &vmstate_pci_device, \
.flags = VMS_STRUCT | VMS_POINTER, \
.offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
}
#endif

1
include/hw/pci/pcie.h
View file

@ -26,7 +26,6 @@
#include "hw/pci/pcie_aer.h"
#include "hw/pci/pcie_sriov.h"
#include "hw/hotplug.h"
#include "hw/pci/pcie_doe.h"
typedef enum {
/* for attention and power indicator */

1
include/hw/pci/pcie_port.h
View file

@ -23,6 +23,7 @@
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_device.h"
#include "qom/object.h"
#define TYPE_PCIE_PORT "pcie-port"

2
include/hw/pci/pcie_sriov.h
View file

@ -13,6 +13,8 @@
#ifndef QEMU_PCIE_SRIOV_H
#define QEMU_PCIE_SRIOV_H
#include "hw/pci/pci.h"
struct PCIESriovPF {
uint16_t num_vfs; /* Number of virtual functions created */
uint8_t vf_bar_type[PCI_NUM_REGIONS]; /* Store type for each VF bar */

2
include/hw/pci/shpc.h
View file

@ -3,7 +3,7 @@
#include "exec/memory.h"
#include "hw/hotplug.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "migration/vmstate.h"
struct SHPCDevice {

2
include/hw/ppc/pnv_psi.h
View file

@ -23,7 +23,7 @@
#include "hw/sysbus.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/xive.h"
#include "qom/object.h"
#include "hw/qdev-core.h"
#define TYPE_PNV_PSI "pnv-psi"
OBJECT_DECLARE_TYPE(PnvPsi, PnvPsiClass,

2
include/hw/remote/iohub.h
View file

@ -11,7 +11,7 @@
#ifndef REMOTE_IOHUB_H
#define REMOTE_IOHUB_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "qemu/event_notifier.h"
#include "qemu/thread-posix.h"
#include "hw/remote/mpqemu-link.h"

2
include/hw/remote/proxy.h
View file

@ -9,7 +9,7 @@
#ifndef PROXY_H
#define PROXY_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "io/channel.h"
#include "hw/remote/proxy-memory-listener.h"
#include "qemu/event_notifier.h"

2
include/hw/riscv/boot_opensbi.h
View file

@ -8,6 +8,8 @@
#ifndef RISCV_BOOT_OPENSBI_H
#define RISCV_BOOT_OPENSBI_H
#include "exec/cpu-defs.h"
/** Expected value of info magic ('OSBI' ascii string in hex) */
#define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f

3
include/hw/riscv/microchip_pfsoc.h
View file

@ -22,13 +22,16 @@
#ifndef HW_MICROCHIP_PFSOC_H
#define HW_MICROCHIP_PFSOC_H
#include "hw/boards.h"
#include "hw/char/mchp_pfsoc_mmuart.h"
#include "hw/cpu/cluster.h"
#include "hw/dma/sifive_pdma.h"
#include "hw/misc/mchp_pfsoc_dmc.h"
#include "hw/misc/mchp_pfsoc_ioscb.h"
#include "hw/misc/mchp_pfsoc_sysreg.h"
#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"
#include "hw/riscv/riscv_hart.h"
typedef struct MicrochipPFSoCState {
/*< private >*/

1
include/hw/riscv/numa.h
View file

@ -19,6 +19,7 @@
#ifndef RISCV_NUMA_H
#define RISCV_NUMA_H
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "sysemu/numa.h"

2
include/hw/riscv/sifive_u.h
View file

@ -19,6 +19,8 @@
#ifndef HW_SIFIVE_U_H
#define HW_SIFIVE_U_H
#include "hw/boards.h"
#include "hw/cpu/cluster.h"
#include "hw/dma/sifive_pdma.h"
#include "hw/net/cadence_gem.h"
#include "hw/riscv/riscv_hart.h"

2
include/hw/riscv/spike.h
View file

@ -19,9 +19,9 @@
#ifndef HW_RISCV_SPIKE_H
#define HW_RISCV_SPIKE_H
#include "hw/boards.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/sysbus.h"
#include "qom/object.h"
#define SPIKE_CPUS_MAX 8
#define SPIKE_SOCKETS_MAX 8

2
include/hw/riscv/virt.h
View file

@ -19,10 +19,10 @@
#ifndef HW_RISCV_VIRT_H
#define HW_RISCV_VIRT_H
#include "hw/boards.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/sysbus.h"
#include "hw/block/flash.h"
#include "qom/object.h"
#define VIRT_CPUS_MAX_BITS 9
#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)

2
include/hw/sd/sdhci.h
View file

@ -25,7 +25,7 @@
#ifndef SDHCI_H
#define SDHCI_H
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/sysbus.h"
#include "hw/sd/sd.h"
#include "qom/object.h"

3
include/hw/southbridge/piix.h
View file

@ -12,8 +12,7 @@
#ifndef HW_SOUTHBRIDGE_PIIX_H
#define HW_SOUTHBRIDGE_PIIX_H
#include "hw/pci/pci.h"
#include "qom/object.h"
#include "hw/pci/pci_device.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60

3
include/hw/ssi/sifive_spi.h
View file

@ -22,6 +22,9 @@
#ifndef HW_SIFIVE_SPI_H
#define HW_SIFIVE_SPI_H
#include "qemu/fifo8.h"
#include "hw/sysbus.h"
#define SIFIVE_SPI_REG_NUM (0x78 / 4)
#define TYPE_SIFIVE_SPI "sifive.spi"

1
include/hw/timer/sse-timer.h
View file

@ -25,6 +25,7 @@
#define SSE_TIMER_H
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "qom/object.h"
#include "hw/timer/sse-counter.h"

1
include/hw/usb/hcd-dwc3.h
View file

@ -26,6 +26,7 @@
#ifndef HCD_DWC3_H
#define HCD_DWC3_H
#include "hw/register.h"
#include "hw/usb/hcd-xhci.h"
#include "hw/usb/hcd-xhci-sysbus.h"

2
include/hw/usb/hcd-musb.h
View file

@ -13,6 +13,8 @@
#ifndef HW_USB_HCD_MUSB_H
#define HW_USB_HCD_MUSB_H
#include "exec/hwaddr.h"
enum musb_irq_source_e {
musb_irq_suspend = 0,
musb_irq_resume,

2
include/hw/usb/xlnx-usb-subsystem.h
View file

@ -25,6 +25,8 @@
#ifndef XLNX_USB_SUBSYSTEM_H
#define XLNX_USB_SUBSYSTEM_H
#include "hw/register.h"
#include "hw/sysbus.h"
#include "hw/usb/xlnx-versal-usb2-ctrl-regs.h"
#include "hw/usb/hcd-dwc3.h"

3
include/hw/usb/xlnx-versal-usb2-ctrl-regs.h
View file

@ -26,6 +26,9 @@
#ifndef XLNX_VERSAL_USB2_CTRL_REGS_H
#define XLNX_VERSAL_USB2_CTRL_REGS_H
#include "hw/register.h"
#include "hw/sysbus.h"
#define TYPE_XILINX_VERSAL_USB2_CTRL_REGS "xlnx.versal-usb2-ctrl-regs"
#define XILINX_VERSAL_USB2_CTRL_REGS(obj) \

3
include/hw/virtio/vhost-backend.h
View file

@ -128,6 +128,8 @@ typedef int (*vhost_get_device_id_op)(struct vhost_dev *dev, uint32_t *dev_id);
typedef bool (*vhost_force_iommu_op)(struct vhost_dev *dev);
typedef int (*vhost_set_config_call_op)(struct vhost_dev *dev,
int fd);
typedef struct VhostOps {
VhostBackendType backend_type;
vhost_backend_init vhost_backend_init;
@ -174,6 +176,7 @@ typedef struct VhostOps {
vhost_vq_get_addr_op vhost_vq_get_addr;
vhost_get_device_id_op vhost_get_device_id;
vhost_force_iommu_op vhost_force_iommu;
vhost_set_config_call_op vhost_set_config_call;
} VhostOps;
int vhost_backend_update_device_iotlb(struct vhost_dev *dev,

2
include/hw/virtio/vhost-vdpa.h
View file

@ -51,6 +51,8 @@ typedef struct vhost_vdpa {
VhostVDPAHostNotifier notifier[VIRTIO_QUEUE_MAX];
} VhostVDPA;
int vhost_vdpa_get_iova_range(int fd, struct vhost_vdpa_iova_range *iova_range);
int vhost_vdpa_dma_map(struct vhost_vdpa *v, uint32_t asid, hwaddr iova,
hwaddr size, void *vaddr, bool readonly);
int vhost_vdpa_dma_unmap(struct vhost_vdpa *v, uint32_t asid, hwaddr iova,

4
include/hw/virtio/vhost.h
View file

@ -33,6 +33,7 @@ struct vhost_virtqueue {
unsigned used_size;
EventNotifier masked_notifier;
EventNotifier error_notifier;
EventNotifier masked_config_notifier;
struct vhost_dev *dev;
};
@ -41,6 +42,7 @@ typedef unsigned long vhost_log_chunk_t;
#define VHOST_LOG_BITS (8 * sizeof(vhost_log_chunk_t))
#define VHOST_LOG_CHUNK (VHOST_LOG_PAGE * VHOST_LOG_BITS)
#define VHOST_INVALID_FEATURE_BIT (0xff)
#define VHOST_QUEUE_NUM_CONFIG_INR 0
struct vhost_log {
unsigned long long size;
@ -187,6 +189,8 @@ int vhost_dev_enable_notifiers(struct vhost_dev *hdev, VirtIODevice *vdev);
* Disable direct notifications to vhost device.
*/
void vhost_dev_disable_notifiers(struct vhost_dev *hdev, VirtIODevice *vdev);
bool vhost_config_pending(struct vhost_dev *hdev);
void vhost_config_mask(struct vhost_dev *hdev, VirtIODevice *vdev, bool mask);
/**
* vhost_dev_is_started() - report status of vhost device

2
include/hw/virtio/virtio-mmio.h
View file

@ -22,8 +22,8 @@
#ifndef HW_VIRTIO_MMIO_H
#define HW_VIRTIO_MMIO_H
#include "hw/sysbus.h"
#include "hw/virtio/virtio-bus.h"
#include "qom/object.h"
/* QOM macros */
/* virtio-mmio-bus */

4
include/hw/virtio/virtio-pci.h
View file

@ -261,5 +261,7 @@ void virtio_pci_types_register(const VirtioPCIDeviceTypeInfo *t);
* @fixed_queues.
*/
unsigned virtio_pci_optimal_num_queues(unsigned fixed_queues);
void virtio_pci_set_guest_notifier_fd_handler(VirtIODevice *vdev, VirtQueue *vq,
int n, bool assign,
bool with_irqfd);
#endif

1
include/hw/virtio/virtio-scsi.h
View file

@ -20,7 +20,6 @@
#define VIRTIO_SCSI_SENSE_SIZE 0
#include "standard-headers/linux/virtio_scsi.h"
#include "hw/virtio/virtio.h"
#include "hw/pci/pci.h"
#include "hw/scsi/scsi.h"
#include "chardev/char-fe.h"
#include "sysemu/iothread.h"

8
include/hw/virtio/virtio.h
View file

@ -22,7 +22,6 @@
#include "standard-headers/linux/virtio_config.h"
#include "standard-headers/linux/virtio_ring.h"
#include "qom/object.h"
#include "hw/virtio/vhost.h"
/*
* A guest should never accept this. It implies negotiation is broken
@ -79,6 +78,9 @@ typedef struct VirtQueueElement
#define VIRTIO_NO_VECTOR 0xffff
/* special index value used internally for config irqs */
#define VIRTIO_CONFIG_IRQ_IDX -1
#define TYPE_VIRTIO_DEVICE "virtio-device"
OBJECT_DECLARE_TYPE(VirtIODevice, VirtioDeviceClass, VIRTIO_DEVICE)
@ -152,6 +154,7 @@ struct VirtIODevice
AddressSpace *dma_as;
QLIST_HEAD(, VirtQueue) *vector_queues;
QTAILQ_ENTRY(VirtIODevice) next;
EventNotifier config_notifier;
};
struct VirtioDeviceClass {
@ -374,6 +377,9 @@ void virtio_queue_aio_attach_host_notifier_no_poll(VirtQueue *vq, AioContext *ct
void virtio_queue_aio_detach_host_notifier(VirtQueue *vq, AioContext *ctx);
VirtQueue *virtio_vector_first_queue(VirtIODevice *vdev, uint16_t vector);
VirtQueue *virtio_vector_next_queue(VirtQueue *vq);
EventNotifier *virtio_config_get_guest_notifier(VirtIODevice *vdev);
void virtio_config_set_guest_notifier_fd_handler(VirtIODevice *vdev,
bool assign, bool with_irqfd);
static inline void virtio_add_feature(uint64_t *features, unsigned int fbit)
{

2
include/hw/xen/xen_common.h
View file

@ -15,7 +15,7 @@
#include "hw/xen/interface/io/xenbus.h"
#include "hw/xen/xen.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "hw/xen/trace.h"
extern xc_interface *xen_xc;