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hw/arm: Attach PSPI module to NPCM8XX SoC

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Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices. Attach it to the NPCM8XX.

Tested:
NPCM8XX PSPI driver probed successfully from dmesg log.

Signed-off-by: Tim Lee <timlee660101@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20250414020629.1867106-1-timlee660101@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Tim Lee 2025-04-14 10:06:29 +08:00 • committed by Peter Maydell
parent cef2274dfa
commit d5df2bb0fa
2 changed files with 12 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

11
hw/arm/npcm8xx.c
View file

@ -67,6 +67,9 @@
/* SDHCI Modules */ /* SDHCI Modules */
#define NPCM8XX_MMC_BA 0xf0842000 #define NPCM8XX_MMC_BA 0xf0842000
/* PSPI Modules */
#define NPCM8XX_PSPI_BA 0xf0201000
/* Run PLL1 at 1600 MHz */ /* Run PLL1 at 1600 MHz */
#define NPCM8XX_PLLCON1_FIXUP_VAL 0x00402101 #define NPCM8XX_PLLCON1_FIXUP_VAL 0x00402101
/* Run the CPU from PLL1 and UART from PLL2 */ /* Run the CPU from PLL1 and UART from PLL2 */
@ -83,6 +86,7 @@ enum NPCM8xxInterrupt {
NPCM8XX_PECI_IRQ = 6, NPCM8XX_PECI_IRQ = 6,
NPCM8XX_KCS_HIB_IRQ = 9, NPCM8XX_KCS_HIB_IRQ = 9,
NPCM8XX_MMC_IRQ = 26, NPCM8XX_MMC_IRQ = 26,
NPCM8XX_PSPI_IRQ = 28,
NPCM8XX_TIMER0_IRQ = 32, /* Timer Module 0 */ NPCM8XX_TIMER0_IRQ = 32, /* Timer Module 0 */
NPCM8XX_TIMER1_IRQ, NPCM8XX_TIMER1_IRQ,
NPCM8XX_TIMER2_IRQ, NPCM8XX_TIMER2_IRQ,
@ -441,6 +445,7 @@ static void npcm8xx_init(Object *obj)
} }
object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
object_initialize_child(obj, "pspi", &s->pspi, TYPE_NPCM_PSPI);
} }
static void npcm8xx_realize(DeviceState *dev, Error **errp) static void npcm8xx_realize(DeviceState *dev, Error **errp)
@ -705,6 +710,11 @@ static void npcm8xx_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
npcm8xx_irq(s, NPCM8XX_MMC_IRQ)); npcm8xx_irq(s, NPCM8XX_MMC_IRQ));
/* PSPI */
sysbus_realize(SYS_BUS_DEVICE(&s->pspi), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pspi), 0, NPCM8XX_PSPI_BA);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pspi), 0,
npcm8xx_irq(s, NPCM8XX_PSPI_IRQ));
create_unimplemented_device("npcm8xx.shm", 0xc0001000, 4 * KiB); create_unimplemented_device("npcm8xx.shm", 0xc0001000, 4 * KiB);
create_unimplemented_device("npcm8xx.gicextra", 0xdfffa000, 24 * KiB); create_unimplemented_device("npcm8xx.gicextra", 0xdfffa000, 24 * KiB);
@ -720,7 +730,6 @@ static void npcm8xx_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("npcm8xx.siox[1]", 0xf0101000, 4 * KiB); create_unimplemented_device("npcm8xx.siox[1]", 0xf0101000, 4 * KiB);
create_unimplemented_device("npcm8xx.siox[2]", 0xf0102000, 4 * KiB); create_unimplemented_device("npcm8xx.siox[2]", 0xf0102000, 4 * KiB);
create_unimplemented_device("npcm8xx.tmps", 0xf0188000, 4 * KiB); create_unimplemented_device("npcm8xx.tmps", 0xf0188000, 4 * KiB);
create_unimplemented_device("npcm8xx.pspi", 0xf0201000, 4 * KiB);
create_unimplemented_device("npcm8xx.viru1", 0xf0204000, 4 * KiB); create_unimplemented_device("npcm8xx.viru1", 0xf0204000, 4 * KiB);
create_unimplemented_device("npcm8xx.viru2", 0xf0205000, 4 * KiB); create_unimplemented_device("npcm8xx.viru2", 0xf0205000, 4 * KiB);
create_unimplemented_device("npcm8xx.jtm1", 0xf0208000, 4 * KiB); create_unimplemented_device("npcm8xx.jtm1", 0xf0208000, 4 * KiB);

2
include/hw/arm/npcm8xx.h
View file

@ -36,6 +36,7 @@
#include "hw/usb/hcd-ehci.h" #include "hw/usb/hcd-ehci.h"
#include "hw/usb/hcd-ohci.h" #include "hw/usb/hcd-ohci.h"
#include "target/arm/cpu.h" #include "target/arm/cpu.h"
#include "hw/ssi/npcm_pspi.h"
#define NPCM8XX_MAX_NUM_CPUS (4) #define NPCM8XX_MAX_NUM_CPUS (4)
@ -99,6 +100,7 @@ struct NPCM8xxState {
OHCISysBusState ohci[2]; OHCISysBusState ohci[2];
NPCM7xxFIUState fiu[3]; NPCM7xxFIUState fiu[3];
NPCM7xxSDHCIState mmc; NPCM7xxSDHCIState mmc;
NPCMPSPIState pspi;
}; };
struct NPCM8xxClass { struct NPCM8xxClass {