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spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE

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This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.

This defines AIL flags for LPCR special register.

This changes @excp_prefix according to the mode, takes effect in TCG.

This turns support of a new capability PPC2_ISA207S flag for TCG.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexey Kardashevskiy 2014-06-04 22:51:05 +10:00 • committed by Alexander Graf
parent c4015bbd50
commit d5ac4f5433
4 changed files with 60 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

47
hw/ppc/spapr_hcall.c
View file

@ -743,6 +743,49 @@ static target_ulong h_set_mode_resouce_le(PowerPCCPU *cpu,
return H_UNSUPPORTED_FLAG; return H_UNSUPPORTED_FLAG;
} }
static target_ulong h_set_mode_resouce_addr_trans_mode(PowerPCCPU *cpu,
target_ulong mflags,
target_ulong value1,
target_ulong value2)
{
CPUState *cs;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
target_ulong prefix;
if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
return H_P2;
}
if (value1) {
return H_P3;
}
if (value2) {
return H_P4;
}
switch (mflags) {
case H_SET_MODE_ADDR_TRANS_NONE:
prefix = 0;
break;
case H_SET_MODE_ADDR_TRANS_0001_8000:
prefix = 0x18000;
break;
case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000:
prefix = 0xC000000000004000;
break;
default:
return H_UNSUPPORTED_FLAG;
}
CPU_FOREACH(cs) {
CPUPPCState *env = &POWERPC_CPU(cpu)->env;
set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL);
env->excp_prefix = prefix;
}
return H_SUCCESS;
}
static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr, static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args) target_ulong opcode, target_ulong *args)
{ {
@ -753,6 +796,10 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
case H_SET_MODE_RESOURCE_LE: case H_SET_MODE_RESOURCE_LE:
ret = h_set_mode_resouce_le(cpu, args[0], args[2], args[3]); ret = h_set_mode_resouce_le(cpu, args[0], args[2], args[3]);
break; break;
case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
ret = h_set_mode_resouce_addr_trans_mode(cpu, args[0],
args[2], args[3]);
break;
} }
return ret; return ret;

5
include/hw/ppc/spapr.h
View file

@ -164,6 +164,11 @@ typedef struct sPAPREnvironment {
#define H_SET_MODE_ENDIAN_BIG 0 #define H_SET_MODE_ENDIAN_BIG 0
#define H_SET_MODE_ENDIAN_LITTLE 1 #define H_SET_MODE_ENDIAN_LITTLE 1
/* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */
#define H_SET_MODE_ADDR_TRANS_NONE 0
#define H_SET_MODE_ADDR_TRANS_0001_8000 2
#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3
/* VASI States */ /* VASI States */
#define H_VASI_INVALID 0 #define H_VASI_INVALID 0
#define H_VASI_ENABLED 1 #define H_VASI_ENABLED 1

4
target-ppc/cpu.h
View file

@ -467,6 +467,8 @@ struct ppc_slb_t {
#define MSR_LE 0 /* Little-endian mode 1 hflags */ #define MSR_LE 0 /* Little-endian mode 1 hflags */
#define LPCR_ILE (1 << (63-38)) #define LPCR_ILE (1 << (63-38))
#define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */
#define LPCR_AIL (3 << LPCR_AIL_SHIFT)
#define msr_sf ((env->msr >> MSR_SF) & 1) #define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1) #define msr_isf ((env->msr >> MSR_ISF) & 1)
@ -2010,7 +2012,7 @@ enum {
PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
PPC2_ALTIVEC_207) PPC2_ALTIVEC_207 | PPC2_ISA207S)
}; };
/*****************************************************************************/ /*****************************************************************************/

7
target-ppc/excp_helper.c
View file

@ -620,8 +620,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
if (asrr1 != -1) { if (asrr1 != -1) {
env->spr[asrr1] = env->spr[srr1]; env->spr[asrr1] = env->spr[srr1];
} }
/* If we disactivated any translation, flush TLBs */
if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) { if (env->spr[SPR_LPCR] & LPCR_AIL) {
new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
} else if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
/* If we disactivated any translation, flush TLBs */
tlb_flush(cs, 1); tlb_flush(cs, 1);
} }