mirror of
https://github.com/Motorhead1991/qemu.git
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target-arm queue:
* fix a bug in bitops.h * implement SD card support on integratorcp * add a missing 'compatible' property for Cortex-A57 * add Netduino 2 machine model * fix command line parsing bug for CPU options with multiple CPUs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJVAE2+AAoJEDwlJe0UNgzeK2wP/j/cMV58i+iZLw5dI3nR5M/J YbM5wWV2VYNJQQcN5rDFGAEzYewGhDYZCjkxWF2AHw5LgpZcSbDlyCsvkRtAv9yR f7E66C+GKx1Mhuvu9ygAy/OqzxC/cmqLbyV46IkeygKT76LLAn/guWyUy7mgbSbA yygMmG3eaaNBJsDdm8YNFbcI3vPecc0fchDe4IsbIiZ1K6wNZH2NVk2+gQ4XXmIn /EIYsczIU5wFsaZ7pMN/adZVKjzVmN7XnG9eeG/3cx/QIis/JFfCU5JuoJ2+BFQW rdeeMtMcg/NUXslADlPpeUTt7gPTeBLxqYYFXPhrdUAmIUA4dh8FjcrUpq4naKj1 cbOQusbJEpkf/La3KgfOy1BjWvK8TmzaFarJcKX4V7x1Lmx0fD4It4l+NwTLnxEV Yel3h0X0/lBGTXUnT5UBfhcj2M9ywl29m+knvVHknfMz3caVyFUNDPnt06rwAiva VgKJ0pgzl98AlSfM1aRpzsoXMYD5DOJLwMry9PEAitWWRRrOdnha7Tm+jWXLNUot izF4i4UJb/J5IED8K2t5iVUWaq5QY7bs3yfWfoCcNpMDoxSHuavxQpiJRwhEeJoH 0HtnAUb5A3tFEdUolrJ88LCfhfZeE0KdjQptXUTesk9VxIGFpjHcZYrPOb9+79m3 oHsE1fY0B4gY+4vI3YgE =HTma -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150311' into staging target-arm queue: * fix a bug in bitops.h * implement SD card support on integratorcp * add a missing 'compatible' property for Cortex-A57 * add Netduino 2 machine model * fix command line parsing bug for CPU options with multiple CPUs # gpg: Signature made Wed Mar 11 14:14:22 2015 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20150311: bitops.h: sextract64() return type should be int64_t, not uint64_t integrator/cp: Implement CARDIN and WPROT signals integrator/cp: Model CP control registers as sysbus device target-arm: Add missing compatible property to A57 netduino2: Add the Netduino 2 Machine stm32f205: Add the stm32f205 SoC stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG stm32f2xx_USART: Add the stm32f2xx USART Controller stm32f2xx_timer: Add the stm32f2xx Timer hw/arm/virt: fix cmdline parsing bug with CPU options and smp > 1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
d598911b6f
18 changed files with 1323 additions and 15 deletions
57
include/hw/arm/stm32f205_soc.h
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57
include/hw/arm/stm32f205_soc.h
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@ -0,0 +1,57 @@
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/*
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* STM32F205 SoC
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_ARM_STM32F205SOC_H
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#define HW_ARM_STM32F205SOC_H
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#include "hw/misc/stm32f2xx_syscfg.h"
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#include "hw/timer/stm32f2xx_timer.h"
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#include "hw/char/stm32f2xx_usart.h"
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#define TYPE_STM32F205_SOC "stm32f205_soc"
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#define STM32F205_SOC(obj) \
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OBJECT_CHECK(STM32F205State, (obj), TYPE_STM32F205_SOC)
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#define STM_NUM_USARTS 6
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#define STM_NUM_TIMERS 4
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#define FLASH_BASE_ADDRESS 0x08000000
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#define FLASH_SIZE (1024 * 1024)
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#define SRAM_BASE_ADDRESS 0x20000000
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#define SRAM_SIZE (128 * 1024)
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typedef struct STM32F205State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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char *kernel_filename;
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char *cpu_model;
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STM32F2XXSyscfgState syscfg;
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STM32F2XXUsartState usart[STM_NUM_USARTS];
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STM32F2XXTimerState timer[STM_NUM_TIMERS];
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} STM32F205State;
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#endif
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73
include/hw/char/stm32f2xx_usart.h
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73
include/hw/char/stm32f2xx_usart.h
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/*
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* STM32F2XX USART
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_STM32F2XX_USART_H
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#define HW_STM32F2XX_USART_H
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#include "hw/sysbus.h"
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#include "sysemu/char.h"
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#include "hw/hw.h"
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#define USART_SR 0x00
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#define USART_DR 0x04
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#define USART_BRR 0x08
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#define USART_CR1 0x0C
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#define USART_CR2 0x10
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#define USART_CR3 0x14
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#define USART_GTPR 0x18
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#define USART_SR_RESET 0x00C00000
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#define USART_SR_TXE (1 << 7)
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#define USART_SR_TC (1 << 6)
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#define USART_SR_RXNE (1 << 5)
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#define USART_CR1_UE (1 << 13)
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#define USART_CR1_RXNEIE (1 << 5)
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#define USART_CR1_TE (1 << 3)
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#define USART_CR1_RE (1 << 2)
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#define TYPE_STM32F2XX_USART "stm32f2xx-usart"
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#define STM32F2XX_USART(obj) \
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OBJECT_CHECK(STM32F2XXUsartState, (obj), TYPE_STM32F2XX_USART)
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typedef struct {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion mmio;
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uint32_t usart_sr;
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uint32_t usart_dr;
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uint32_t usart_brr;
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uint32_t usart_cr1;
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uint32_t usart_cr2;
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uint32_t usart_cr3;
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uint32_t usart_gtpr;
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CharDriverState *chr;
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qemu_irq irq;
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} STM32F2XXUsartState;
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#endif /* HW_STM32F2XX_USART_H */
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61
include/hw/misc/stm32f2xx_syscfg.h
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61
include/hw/misc/stm32f2xx_syscfg.h
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/*
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* STM32F2XX SYSCFG
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_STM32F2XX_SYSCFG_H
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#define HW_STM32F2XX_SYSCFG_H
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#include "hw/sysbus.h"
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#include "hw/hw.h"
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#define SYSCFG_MEMRMP 0x00
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#define SYSCFG_PMC 0x04
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#define SYSCFG_EXTICR1 0x08
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#define SYSCFG_EXTICR2 0x0C
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#define SYSCFG_EXTICR3 0x10
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#define SYSCFG_EXTICR4 0x14
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#define SYSCFG_CMPCR 0x20
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#define TYPE_STM32F2XX_SYSCFG "stm32f2xx-syscfg"
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#define STM32F2XX_SYSCFG(obj) \
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OBJECT_CHECK(STM32F2XXSyscfgState, (obj), TYPE_STM32F2XX_SYSCFG)
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typedef struct {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion mmio;
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uint32_t syscfg_memrmp;
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uint32_t syscfg_pmc;
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uint32_t syscfg_exticr1;
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uint32_t syscfg_exticr2;
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uint32_t syscfg_exticr3;
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uint32_t syscfg_exticr4;
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uint32_t syscfg_cmpcr;
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qemu_irq irq;
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} STM32F2XXSyscfgState;
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#endif /* HW_STM32F2XX_SYSCFG_H */
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101
include/hw/timer/stm32f2xx_timer.h
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101
include/hw/timer/stm32f2xx_timer.h
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/*
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* STM32F2XX Timer
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_STM32F2XX_TIMER_H
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#define HW_STM32F2XX_TIMER_H
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#define TIM_CR1 0x00
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#define TIM_CR2 0x04
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#define TIM_SMCR 0x08
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#define TIM_DIER 0x0C
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#define TIM_SR 0x10
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#define TIM_EGR 0x14
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#define TIM_CCMR1 0x18
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#define TIM_CCMR2 0x1C
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#define TIM_CCER 0x20
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#define TIM_CNT 0x24
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#define TIM_PSC 0x28
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#define TIM_ARR 0x2C
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#define TIM_CCR1 0x34
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#define TIM_CCR2 0x38
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#define TIM_CCR3 0x3C
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#define TIM_CCR4 0x40
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#define TIM_DCR 0x48
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#define TIM_DMAR 0x4C
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#define TIM_OR 0x50
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#define TIM_CR1_CEN 1
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#define TIM_EGR_UG 1
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#define TIM_CCER_CC2E (1 << 4)
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#define TIM_CCMR1_OC2M2 (1 << 14)
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#define TIM_CCMR1_OC2M1 (1 << 13)
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#define TIM_CCMR1_OC2M0 (1 << 12)
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#define TIM_CCMR1_OC2PE (1 << 11)
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#define TIM_DIER_UIE 1
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#define TYPE_STM32F2XX_TIMER "stm32f2xx-timer"
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#define STM32F2XXTIMER(obj) OBJECT_CHECK(STM32F2XXTimerState, \
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(obj), TYPE_STM32F2XX_TIMER)
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typedef struct STM32F2XXTimerState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion iomem;
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QEMUTimer *timer;
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qemu_irq irq;
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int64_t tick_offset;
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uint64_t hit_time;
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uint64_t freq_hz;
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uint32_t tim_cr1;
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uint32_t tim_cr2;
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uint32_t tim_smcr;
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uint32_t tim_dier;
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uint32_t tim_sr;
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uint32_t tim_egr;
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uint32_t tim_ccmr1;
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uint32_t tim_ccmr2;
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uint32_t tim_ccer;
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uint32_t tim_psc;
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uint32_t tim_arr;
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uint32_t tim_ccr1;
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uint32_t tim_ccr2;
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uint32_t tim_ccr3;
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uint32_t tim_ccr4;
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uint32_t tim_dcr;
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uint32_t tim_dmar;
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uint32_t tim_or;
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} STM32F2XXTimerState;
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#endif /* HW_STM32F2XX_TIMER_H */
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