mirror of
https://github.com/Motorhead1991/qemu.git
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target-arm queue:
* fix a bug in bitops.h * implement SD card support on integratorcp * add a missing 'compatible' property for Cortex-A57 * add Netduino 2 machine model * fix command line parsing bug for CPU options with multiple CPUs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJVAE2+AAoJEDwlJe0UNgzeK2wP/j/cMV58i+iZLw5dI3nR5M/J YbM5wWV2VYNJQQcN5rDFGAEzYewGhDYZCjkxWF2AHw5LgpZcSbDlyCsvkRtAv9yR f7E66C+GKx1Mhuvu9ygAy/OqzxC/cmqLbyV46IkeygKT76LLAn/guWyUy7mgbSbA yygMmG3eaaNBJsDdm8YNFbcI3vPecc0fchDe4IsbIiZ1K6wNZH2NVk2+gQ4XXmIn /EIYsczIU5wFsaZ7pMN/adZVKjzVmN7XnG9eeG/3cx/QIis/JFfCU5JuoJ2+BFQW rdeeMtMcg/NUXslADlPpeUTt7gPTeBLxqYYFXPhrdUAmIUA4dh8FjcrUpq4naKj1 cbOQusbJEpkf/La3KgfOy1BjWvK8TmzaFarJcKX4V7x1Lmx0fD4It4l+NwTLnxEV Yel3h0X0/lBGTXUnT5UBfhcj2M9ywl29m+knvVHknfMz3caVyFUNDPnt06rwAiva VgKJ0pgzl98AlSfM1aRpzsoXMYD5DOJLwMry9PEAitWWRRrOdnha7Tm+jWXLNUot izF4i4UJb/J5IED8K2t5iVUWaq5QY7bs3yfWfoCcNpMDoxSHuavxQpiJRwhEeJoH 0HtnAUb5A3tFEdUolrJ88LCfhfZeE0KdjQptXUTesk9VxIGFpjHcZYrPOb9+79m3 oHsE1fY0B4gY+4vI3YgE =HTma -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150311' into staging target-arm queue: * fix a bug in bitops.h * implement SD card support on integratorcp * add a missing 'compatible' property for Cortex-A57 * add Netduino 2 machine model * fix command line parsing bug for CPU options with multiple CPUs # gpg: Signature made Wed Mar 11 14:14:22 2015 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20150311: bitops.h: sextract64() return type should be int64_t, not uint64_t integrator/cp: Implement CARDIN and WPROT signals integrator/cp: Model CP control registers as sysbus device target-arm: Add missing compatible property to A57 netduino2: Add the Netduino 2 Machine stm32f205: Add the stm32f205 SoC stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG stm32f2xx_USART: Add the stm32f2xx USART Controller stm32f2xx_timer: Add the stm32f2xx Timer hw/arm/virt: fix cmdline parsing bug with CPU options and smp > 1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
d598911b6f
18 changed files with 1323 additions and 15 deletions
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@ -15,6 +15,7 @@ obj-$(CONFIG_OMAP) += omap_uart.o
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obj-$(CONFIG_SH4) += sh_serial.o
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obj-$(CONFIG_PSERIES) += spapr_vty.o
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obj-$(CONFIG_DIGIC) += digic-uart.o
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obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
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common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
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common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o
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229
hw/char/stm32f2xx_usart.c
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229
hw/char/stm32f2xx_usart.c
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@ -0,0 +1,229 @@
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/*
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* STM32F2XX USART
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/char/stm32f2xx_usart.h"
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#ifndef STM_USART_ERR_DEBUG
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#define STM_USART_ERR_DEBUG 0
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#endif
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#define DB_PRINT_L(lvl, fmt, args...) do { \
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if (STM_USART_ERR_DEBUG >= lvl) { \
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qemu_log("%s: " fmt, __func__, ## args); \
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} \
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} while (0);
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#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
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static int stm32f2xx_usart_can_receive(void *opaque)
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{
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STM32F2XXUsartState *s = opaque;
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if (!(s->usart_sr & USART_SR_RXNE)) {
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return 1;
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}
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return 0;
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}
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static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
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{
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STM32F2XXUsartState *s = opaque;
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s->usart_dr = *buf;
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if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
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/* USART not enabled - drop the chars */
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DB_PRINT("Dropping the chars\n");
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return;
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}
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s->usart_sr |= USART_SR_RXNE;
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if (s->usart_cr1 & USART_CR1_RXNEIE) {
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qemu_set_irq(s->irq, 1);
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}
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DB_PRINT("Receiving: %c\n", s->usart_dr);
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}
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static void stm32f2xx_usart_reset(DeviceState *dev)
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{
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STM32F2XXUsartState *s = STM32F2XX_USART(dev);
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s->usart_sr = USART_SR_RESET;
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s->usart_dr = 0x00000000;
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s->usart_brr = 0x00000000;
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s->usart_cr1 = 0x00000000;
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s->usart_cr2 = 0x00000000;
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s->usart_cr3 = 0x00000000;
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s->usart_gtpr = 0x00000000;
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qemu_set_irq(s->irq, 0);
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}
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static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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STM32F2XXUsartState *s = opaque;
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uint64_t retvalue;
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DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
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switch (addr) {
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case USART_SR:
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retvalue = s->usart_sr;
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s->usart_sr &= ~USART_SR_TC;
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if (s->chr) {
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qemu_chr_accept_input(s->chr);
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}
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return retvalue;
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case USART_DR:
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DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
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s->usart_sr |= USART_SR_TXE;
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s->usart_sr &= ~USART_SR_RXNE;
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if (s->chr) {
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qemu_chr_accept_input(s->chr);
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}
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qemu_set_irq(s->irq, 0);
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return s->usart_dr & 0x3FF;
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case USART_BRR:
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return s->usart_brr;
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case USART_CR1:
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return s->usart_cr1;
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case USART_CR2:
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return s->usart_cr2;
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case USART_CR3:
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return s->usart_cr3;
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case USART_GTPR:
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return s->usart_gtpr;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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return 0;
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}
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return 0;
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}
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static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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STM32F2XXUsartState *s = opaque;
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uint32_t value = val64;
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unsigned char ch;
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DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
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switch (addr) {
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case USART_SR:
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if (value <= 0x3FF) {
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s->usart_sr = value;
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} else {
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s->usart_sr &= value;
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}
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if (!(s->usart_sr & USART_SR_RXNE)) {
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qemu_set_irq(s->irq, 0);
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}
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return;
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case USART_DR:
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if (value < 0xF000) {
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ch = value;
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if (s->chr) {
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qemu_chr_fe_write_all(s->chr, &ch, 1);
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}
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s->usart_sr |= USART_SR_TC;
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s->usart_sr &= ~USART_SR_TXE;
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}
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return;
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case USART_BRR:
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s->usart_brr = value;
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return;
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case USART_CR1:
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s->usart_cr1 = value;
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if (s->usart_cr1 & USART_CR1_RXNEIE &&
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s->usart_sr & USART_SR_RXNE) {
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qemu_set_irq(s->irq, 1);
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}
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return;
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case USART_CR2:
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s->usart_cr2 = value;
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return;
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case USART_CR3:
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s->usart_cr3 = value;
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return;
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case USART_GTPR:
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s->usart_gtpr = value;
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return;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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}
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}
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static const MemoryRegionOps stm32f2xx_usart_ops = {
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.read = stm32f2xx_usart_read,
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.write = stm32f2xx_usart_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void stm32f2xx_usart_init(Object *obj)
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{
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STM32F2XXUsartState *s = STM32F2XX_USART(obj);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
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TYPE_STM32F2XX_USART, 0x2000);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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s->chr = qemu_char_get_next_serial();
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if (s->chr) {
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qemu_chr_add_handlers(s->chr, stm32f2xx_usart_can_receive,
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stm32f2xx_usart_receive, NULL, s);
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}
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}
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static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = stm32f2xx_usart_reset;
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}
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static const TypeInfo stm32f2xx_usart_info = {
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.name = TYPE_STM32F2XX_USART,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(STM32F2XXUsartState),
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.instance_init = stm32f2xx_usart_init,
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.class_init = stm32f2xx_usart_class_init,
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};
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static void stm32f2xx_usart_register_types(void)
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{
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type_register_static(&stm32f2xx_usart_info);
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}
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type_init(stm32f2xx_usart_register_types)
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