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Unify IRQ handling.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2007-04-07 18:14:41 +00:00
parent b6e27ab8b1
commit d537cf6c86
71 changed files with 592 additions and 624 deletions
Download patch file Download diff file Expand all files Collapse all files

46
hw/versatilepb.c
View file

@ -14,12 +14,11 @@
typedef struct vpb_sic_state
{
arm_pic_handler handler;
uint32_t base;
uint32_t level;
uint32_t mask;
uint32_t pic_enable;
void *parent;
qemu_irq *parent;
int irq;
} vpb_sic_state;
@ -28,7 +27,7 @@ static void vpb_sic_update(vpb_sic_state *s)
uint32_t flags;
flags = s->level & s->mask;
pic_set_irq_new(s->parent, s->irq, flags != 0);
qemu_set_irq(s->parent[s->irq], flags != 0);
}
static void vpb_sic_update_pic(vpb_sic_state *s)
@ -40,7 +39,7 @@ static void vpb_sic_update_pic(vpb_sic_state *s)
mask = 1u << i;
if (!(s->pic_enable & mask))
continue;
pic_set_irq_new(s->parent, i, (s->level & mask) != 0);
qemu_set_irq(s->parent[i], (s->level & mask) != 0);
}
}
@ -52,7 +51,7 @@ static void vpb_sic_set_irq(void *opaque, int irq, int level)
else
s->level &= ~(1u << irq);
if (s->pic_enable & (1u << irq))
pic_set_irq_new(s->parent, irq, level);
qemu_set_irq(s->parent[irq], level);
vpb_sic_update(s);
}
@ -126,15 +125,16 @@ static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
vpb_sic_write
};
static vpb_sic_state *vpb_sic_init(uint32_t base, void *parent, int irq)
static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
{
vpb_sic_state *s;
qemu_irq *qi;
int iomemtype;
s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
if (!s)
return NULL;
s->handler = vpb_sic_set_irq;
qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
s->base = base;
s->parent = parent;
s->irq = irq;
@ -142,7 +142,7 @@ static vpb_sic_state *vpb_sic_init(uint32_t base, void *parent, int irq)
vpb_sic_writefn, s);
cpu_register_physical_memory(base, 0x00000fff, iomemtype);
/* ??? Save/restore. */
return s;
return qi;
}
/* Board init. */
@ -158,8 +158,8 @@ static void versatile_init(int ram_size, int vga_ram_size, int boot_device,
int board_id)
{
CPUState *env;
void *pic;
void *sic;
qemu_irq *pic;
qemu_irq *sic;
void *scsi_hba;
PCIBus *pci_bus;
NICInfo *nd;
@ -176,10 +176,10 @@ static void versatile_init(int ram_size, int vga_ram_size, int boot_device,
arm_sysctl_init(0x10000000, 0x41007004);
pic = arm_pic_init_cpu(env);
pic = pl190_init(0x10140000, pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
pic = pl190_init(0x10140000, pic[0], pic[1]);
sic = vpb_sic_init(0x10003000, pic, 31);
pl050_init(0x10006000, sic, 3, 0);
pl050_init(0x10007000, sic, 4, 1);
pl050_init(0x10006000, sic[3], 0);
pl050_init(0x10007000, sic[4], 1);
pci_bus = pci_vpb_init(sic, 27, 0);
/* The Versatile PCI bridge does not provide access to PCI IO space,
@ -189,7 +189,7 @@ static void versatile_init(int ram_size, int vga_ram_size, int boot_device,
if (!nd->model)
nd->model = done_smc ? "rtl8139" : "smc91c111";
if (strcmp(nd->model, "smc91c111") == 0) {
smc91c111_init(nd, 0x10010000, sic, 25);
smc91c111_init(nd, 0x10010000, sic[25]);
} else {
pci_nic_init(pci_bus, nd, -1);
}
@ -204,20 +204,20 @@ static void versatile_init(int ram_size, int vga_ram_size, int boot_device,
}
}
pl011_init(0x101f1000, pic, 12, serial_hds[0]);
pl011_init(0x101f2000, pic, 13, serial_hds[1]);
pl011_init(0x101f3000, pic, 14, serial_hds[2]);
pl011_init(0x10009000, sic, 6, serial_hds[3]);
pl011_init(0x101f1000, pic[12], serial_hds[0]);
pl011_init(0x101f2000, pic[13], serial_hds[1]);
pl011_init(0x101f3000, pic[14], serial_hds[2]);
pl011_init(0x10009000, sic[6], serial_hds[3]);
pl080_init(0x10130000, pic, 17, 8);
sp804_init(0x101e2000, pic, 4);
sp804_init(0x101e3000, pic, 5);
pl080_init(0x10130000, pic[17], 8);
sp804_init(0x101e2000, pic[4]);
sp804_init(0x101e3000, pic[5]);
/* The versatile/PB actually has a modified Color LCD controller
that includes hardware cursor support from the PL111. */
pl110_init(ds, 0x10120000, pic, 16, 1);
pl110_init(ds, 0x10120000, pic[16], 1);
pl181_init(0x10005000, sd_bdrv, sic, 22, 1);
pl181_init(0x10005000, sd_bdrv, sic[22], sic[1]);
#if 0
/* Disabled because there's no way of specifying a block device. */
pl181_init(0x1000b000, NULL, sic, 23, 2);