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accel/tcg: Add 'size' param to probe_access_full
Change to match the recent change to probe_access_flags. All existing callers updated to supply 0, so no change in behaviour. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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1770b2f2d3
commit
d507e6c565
7 changed files with 10 additions and 10 deletions
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@ -118,7 +118,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
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* valid. Indicate to probe_access_flags no-fault, then assert that
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* we received a valid page.
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*/
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flags = probe_access_full(env, ptr, ptr_access, ptr_mmu_idx,
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flags = probe_access_full(env, ptr, 0, ptr_access, ptr_mmu_idx,
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ra == 0, &host, &full, ra);
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assert(!(flags & TLB_INVALID_MASK));
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@ -154,7 +154,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
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*/
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in_page = -(ptr | TARGET_PAGE_MASK);
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if (unlikely(ptr_size > in_page)) {
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flags |= probe_access_full(env, ptr + in_page, ptr_access,
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flags |= probe_access_full(env, ptr + in_page, 0, ptr_access,
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ptr_mmu_idx, ra == 0, &host, &full, ra);
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assert(!(flags & TLB_INVALID_MASK));
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}
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@ -5356,7 +5356,7 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
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&info->host, retaddr);
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#else
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CPUTLBEntryFull *full;
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flags = probe_access_full(env, addr, access_type, mmu_idx, nofault,
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flags = probe_access_full(env, addr, 0, access_type, mmu_idx, nofault,
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&info->host, &full, retaddr);
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#endif
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info->flags = flags;
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@ -14651,7 +14651,7 @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s)
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* that the TLB entry must be present and valid, and thus this
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* access will never raise an exception.
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*/
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flags = probe_access_full(env, addr, MMU_INST_FETCH, mmu_idx,
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flags = probe_access_full(env, addr, 0, MMU_INST_FETCH, mmu_idx,
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false, &host, &full, 0);
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assert(!(flags & TLB_INVALID_MASK));
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