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aspeed: Fix maximum number of spi controller

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Commit 6de4aa8dc5 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700
A1") extends ast2700a1 spis_num to 3, but ASPEED_SPIS_NUM defines the
maximum number of spi controller to 2, result in ehci[0] is being
overwritten in runtime.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Fixes: 6de4aa8dc5 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1")
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250317065938.1902272-1-troy_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Troy Lee 2025-03-17 14:59:37 +08:00 • committed by Cédric Le Goater
parent 527dede083
commit d4dfb4ffd4
1 changed files with 1 additions and 1 deletions
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2
include/hw/arm/aspeed_soc.h
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@ -42,7 +42,7 @@
#include "hw/char/serial-mm.h"
#include "hw/intc/arm_gicv3.h"
#define ASPEED_SPIS_NUM 2
#define ASPEED_SPIS_NUM 3
#define ASPEED_EHCIS_NUM 2
#define ASPEED_WDTS_NUM 8
#define ASPEED_CPUS_NUM 4