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hw/opentitan: Update the interrupt layout

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Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-03-31 11:00:11 -04:00
parent ab2c91286c
commit d4cad54499
3 changed files with 22 additions and 22 deletions
Download patch file Download diff file Expand all files Collapse all files

16
include/hw/riscv/opentitan.h
View file

@ -82,14 +82,14 @@ enum {
};
enum {
IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
IBEX_UART_TX_EMPTY_IRQ = 0x23,
IBEX_UART_RX_WATERMARK_IRQ = 0x22,
IBEX_UART_TX_WATERMARK_IRQ = 0x21,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
IBEX_UART0_RX_OVERFLOW_IRQ = 4,
IBEX_UART0_TX_EMPTY_IRQ = 3,
IBEX_UART0_RX_WATERMARK_IRQ = 2,
IBEX_UART0_TX_WATERMARK_IRQ = 1,
};
#endif