motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-06 17:23:56 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

tcg: Split out tcg-target-reg-bits.h

Browse source 
Often, the only thing we need to know about the TCG host
is the register size.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-05-01 10:57:11 +01:00
parent e5b4906377
commit d46259c037
18 changed files with 162 additions and 59 deletions
Download patch file Download diff file Expand all files Collapse all files

19
tcg/riscv/tcg-target-reg-bits.h Normal file
View file

@ -0,0 +1,19 @@
/* SPDX-License-Identifier: MIT */
/*
* Define target-specific register size
* Copyright (c) 2018 SiFive, Inc
*/
#ifndef TCG_TARGET_REG_BITS_H
#define TCG_TARGET_REG_BITS_H
/*
* We don't support oversize guests.
* Since we will only build tcg once, this in turn requires a 64-bit host.
*/
#if __riscv_xlen != 64
#error "unsupported code generation mode"
#endif
#define TCG_TARGET_REG_BITS 64
#endif

9
tcg/riscv/tcg-target.h
View file

@ -25,15 +25,6 @@
#ifndef RISCV_TCG_TARGET_H
#define RISCV_TCG_TARGET_H
/*
* We don't support oversize guests.
* Since we will only build tcg once, this in turn requires a 64-bit host.
*/
#if __riscv_xlen != 64
#error "unsupported code generation mode"
#endif
#define TCG_TARGET_REG_BITS 64
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_NB_REGS 32
#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)