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tcg: Convert xor to TCGOutOpBinary

Browse source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-06 15:11:22 -08:00
parent 6aba25ebb9
commit d3e56f3824
11 changed files with 186 additions and 104 deletions
Download patch file Download diff file Expand all files Collapse all files

31
tcg/aarch64/tcg-target.c.inc
View file

@ -2186,6 +2186,24 @@ static const TCGOutOpBinary outop_orc = {
.out_rrr = tgen_orc, .out_rrr = tgen_orc,
}; };
static void tgen_xor(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_insn(s, 3510, EOR, type, a0, a1, a2);
}
static void tgen_xori(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_logicali(s, I3404_EORI, type, a0, a1, a2);
}
static const TCGOutOpBinary outop_xor = {
.base.static_constraint = C_O1_I2(r, r, rL),
.out_rrr = tgen_xor,
.out_rri = tgen_xori,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -2267,17 +2285,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1); tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
break; break;
case INDEX_op_xor_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
case INDEX_op_xor_i64:
if (c2) {
tcg_out_logicali(s, I3404_EORI, ext, a0, a1, a2);
} else {
tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2);
}
break;
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
a2 = (int32_t)a2; a2 = (int32_t)a2;
/* FALLTHRU */ /* FALLTHRU */
@ -3023,8 +3030,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_mulsh_i64: case INDEX_op_mulsh_i64:
return C_O1_I2(r, r, r); return C_O1_I2(r, r, r);
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64: case INDEX_op_eqv_i64:
return C_O1_I2(r, r, rL); return C_O1_I2(r, r, rL);

25
tcg/arm/tcg-target.c.inc
View file

@ -1903,6 +1903,24 @@ static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_NotImplemented, .base.static_constraint = C_NotImplemented,
}; };
static void tgen_xor(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_dat_reg(s, COND_AL, ARITH_EOR, a0, a1, a2, SHIFT_IMM_LSL(0));
}
static void tgen_xori(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_dat_imm(s, COND_AL, ARITH_EOR, a0, a1, encode_imm_nofail(a2));
}
static const TCGOutOpBinary outop_xor = {
.base.static_constraint = C_O1_I2(r, r, rI),
.out_rrr = tgen_xor,
.out_rri = tgen_xori,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -1965,10 +1983,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
args[0], args[1], args[2], const_args[2]); args[0], args[1], args[2], const_args[2]);
} }
break; break;
case INDEX_op_xor_i32:
c = ARITH_EOR;
tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]);
break;
case INDEX_op_add2_i32: case INDEX_op_add2_i32:
a0 = args[0], a1 = args[1], a2 = args[2]; a0 = args[0], a1 = args[1], a2 = args[2];
a3 = args[3], a4 = args[4], a5 = args[5]; a3 = args[3], a4 = args[4], a5 = args[5];
@ -2226,9 +2240,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_muls2_i32: case INDEX_op_muls2_i32:
return C_O2_I2(r, r, r, r); return C_O2_I2(r, r, r, r);
case INDEX_op_xor_i32:
return C_O1_I2(r, r, rI);
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
case INDEX_op_shr_i32: case INDEX_op_shr_i32:
case INDEX_op_sar_i32: case INDEX_op_sar_i32:

27
tcg/i386/tcg-target.c.inc
View file

@ -2657,6 +2657,26 @@ static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_NotImplemented, .base.static_constraint = C_NotImplemented,
}; };
static void tgen_xor(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
tgen_arithr(s, ARITH_XOR + rexw, a0, a2);
}
static void tgen_xori(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
tgen_arithi(s, ARITH_XOR + rexw, a0, a2, false);
}
static const TCGOutOpBinary outop_xor = {
.base.static_constraint = C_O1_I2(r, 0, re),
.out_rrr = tgen_xor,
.out_rri = tgen_xori,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -2740,11 +2760,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
OP_32_64(sub): OP_32_64(sub):
c = ARITH_SUB; c = ARITH_SUB;
goto gen_arith;
OP_32_64(xor):
c = ARITH_XOR;
goto gen_arith;
gen_arith:
if (const_a2) { if (const_a2) {
tgen_arithi(s, c + rexw, a0, a2, 0); tgen_arithi(s, c + rexw, a0, a2, 0);
} else { } else {
@ -3666,8 +3681,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_sub_i64: case INDEX_op_sub_i64:
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
case INDEX_op_mul_i64: case INDEX_op_mul_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
return C_O1_I2(r, 0, re); return C_O1_I2(r, 0, re);
case INDEX_op_shl_i32: case INDEX_op_shl_i32:

29
tcg/loongarch64/tcg-target.c.inc
View file

@ -1357,6 +1357,24 @@ static const TCGOutOpBinary outop_orc = {
.out_rrr = tgen_orc, .out_rrr = tgen_orc,
}; };
static void tgen_xor(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_opc_xor(s, a0, a1, a2);
}
static void tgen_xori(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_opc_xori(s, a0, a1, a2);
}
static const TCGOutOpBinary outop_xor = {
.base.static_constraint = C_O1_I2(r, r, rU),
.out_rrr = tgen_xor,
.out_rri = tgen_xori,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -1407,15 +1425,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
break; break;
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
if (c2) {
tcg_out_opc_xori(s, a0, a1, a2);
} else {
tcg_out_opc_xor(s, a0, a1, a2);
}
break;
case INDEX_op_extract_i32: case INDEX_op_extract_i32:
if (a2 == 0 && args[3] <= 12) { if (a2 == 0 && args[3] <= 12) {
tcg_out_opc_andi(s, a0, a1, (1 << args[3]) - 1); tcg_out_opc_andi(s, a0, a1, (1 << args[3]) - 1);
@ -2297,8 +2306,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_nor_i32: case INDEX_op_nor_i32:
case INDEX_op_nor_i64: case INDEX_op_nor_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
/* LoongArch reg-imm bitops have their imms ZERO-extended */ /* LoongArch reg-imm bitops have their imms ZERO-extended */
return C_O1_I2(r, r, rU); return C_O1_I2(r, r, rU);

28
tcg/mips/tcg-target.c.inc
View file

@ -1734,6 +1734,24 @@ static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_NotImplemented, .base.static_constraint = C_NotImplemented,
}; };
static void tgen_xor(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
}
static void tgen_xori(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
}
static const TCGOutOpBinary outop_xor = {
.base.static_constraint = C_O1_I2(r, r, rI),
.out_rrr = tgen_xor,
.out_rri = tgen_xori,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -1807,13 +1825,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_ldst(s, i1, a0, a1, a2); tcg_out_ldst(s, i1, a0, a1, a2);
break; break;
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
i1 = OPC_XOR, i2 = OPC_XORI;
if (c2) {
tcg_out_opc_imm(s, i2, a0, a1, a2);
break;
}
do_binaryv: do_binaryv:
tcg_out_opc_reg(s, i1, a0, a1, a2); tcg_out_opc_reg(s, i1, a0, a1, a2);
break; break;
@ -2235,9 +2246,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_muls2_i64: case INDEX_op_muls2_i64:
case INDEX_op_mulu2_i64: case INDEX_op_mulu2_i64:
return C_O2_I2(r, r, r, r); return C_O2_I2(r, r, r, r);
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
return C_O1_I2(r, r, rI);
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
case INDEX_op_shr_i32: case INDEX_op_shr_i32:
case INDEX_op_sar_i32: case INDEX_op_sar_i32:

30
tcg/ppc/tcg-target.c.inc
View file

@ -2983,6 +2983,24 @@ static const TCGOutOpBinary outop_orc = {
.out_rrr = tgen_orc, .out_rrr = tgen_orc,
}; };
static void tgen_xor(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out32(s, XOR | SAB(a1, a0, a2));
}
static void tgen_xori(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_xori32(s, a0, a1, a2);
}
static const TCGOutOpBinary outop_xor = {
.base.static_constraint = C_O1_I2(r, r, rU),
.out_rrr = tgen_xor,
.out_rri = tgen_xori,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -3068,15 +3086,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
break; break;
case INDEX_op_xor_i64:
case INDEX_op_xor_i32:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_xori32(s, a0, a1, a2);
} else {
tcg_out32(s, XOR | SAB(a1, a0, a2));
}
break;
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
if (const_args[2]) { if (const_args[2]) {
tcg_out_xori32(s, args[0], args[1], ~args[2]); tcg_out_xori32(s, args[0], args[1], ~args[2]);
@ -4141,7 +4150,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st_i64: case INDEX_op_st_i64:
return C_O0_I2(r, r); return C_O0_I2(r, r);
case INDEX_op_xor_i32:
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
case INDEX_op_shr_i32: case INDEX_op_shr_i32:
@ -4180,8 +4188,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_sub_i32: case INDEX_op_sub_i32:
return C_O1_I2(r, rI, ri); return C_O1_I2(r, rI, ri);
case INDEX_op_xor_i64:
return C_O1_I2(r, r, rU);
case INDEX_op_sub_i64: case INDEX_op_sub_i64:
return C_O1_I2(r, rI, rT); return C_O1_I2(r, rI, rT);
case INDEX_op_clz_i32: case INDEX_op_clz_i32:

29
tcg/riscv/tcg-target.c.inc
View file

@ -2043,6 +2043,24 @@ static const TCGOutOpBinary outop_orc = {
.out_rrr = tgen_orc, .out_rrr = tgen_orc,
}; };
static void tgen_xor(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
}
static void tgen_xori(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
}
static const TCGOutOpBinary outop_xor = {
.base.static_constraint = C_O1_I2(r, r, rI),
.out_rrr = tgen_xor,
.out_rri = tgen_xori,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -2121,15 +2139,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
break; break;
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
} else {
tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
}
break;
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64: case INDEX_op_eqv_i64:
if (c2) { if (c2) {
@ -2695,8 +2704,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st_i64: case INDEX_op_st_i64:
return C_O0_I2(rz, r); return C_O0_I2(rz, r);
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
case INDEX_op_setcond_i32: case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64: case INDEX_op_setcond_i64:
case INDEX_op_negsetcond_i32: case INDEX_op_negsetcond_i32:

50
tcg/s390x/tcg-target.c.inc
View file

@ -2283,6 +2283,31 @@ static const TCGOutOpBinary outop_orc = {
.out_rrr = tgen_orc, .out_rrr = tgen_orc,
}; };
static void tgen_xor(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
if (type != TCG_TYPE_I32) {
tcg_out_insn(s, RRFa, XGRK, a0, a1, a2);
} else if (a0 == a1) {
tcg_out_insn(s, RR, XR, a0, a2);
} else {
tcg_out_insn(s, RRFa, XRK, a0, a1, a2);
}
}
static void tgen_xori_3(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_mov(s, type, a0, a1);
tgen_xori(s, a0, type == TCG_TYPE_I32 ? (uint32_t)a2 : a2);
}
static const TCGOutOpBinary outop_xor = {
.base.static_constraint = C_O1_I2(r, r, rK),
.out_rrr = tgen_xor,
.out_rri = tgen_xori_3,
};
# define OP_32_64(x) \ # define OP_32_64(x) \
case glue(glue(INDEX_op_,x),_i32): \ case glue(glue(INDEX_op_,x),_i32): \
@ -2351,18 +2376,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
break; break;
case INDEX_op_xor_i32:
a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
if (const_args[2]) {
tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
tcg_out_insn(s, RIL, XILF, a0, a2);
} else if (a0 == a1) {
tcg_out_insn(s, RR, XR, args[0], args[2]);
} else {
tcg_out_insn(s, RRFa, XRK, a0, a1, a2);
}
break;
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
if (const_args[2]) { if (const_args[2]) {
@ -2582,16 +2595,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
break; break;
case INDEX_op_xor_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
tgen_xori(s, a0, a2);
} else {
tcg_out_insn(s, RRFa, XGRK, a0, a1, a2);
}
break;
case INDEX_op_eqv_i64: case INDEX_op_eqv_i64:
a0 = args[0], a1 = args[1], a2 = args[2]; a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) { if (const_args[2]) {
@ -3285,10 +3288,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_sub_i32: case INDEX_op_sub_i32:
case INDEX_op_sub_i64: case INDEX_op_sub_i64:
case INDEX_op_xor_i32:
return C_O1_I2(r, r, ri); return C_O1_I2(r, r, ri);
case INDEX_op_xor_i64:
return C_O1_I2(r, r, rK);
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
return C_O1_I2(r, r, ri); return C_O1_I2(r, r, ri);

23
tcg/sparc64/tcg-target.c.inc
View file

@ -1362,6 +1362,24 @@ static const TCGOutOpBinary outop_orc = {
.out_rrr = tgen_orc, .out_rrr = tgen_orc,
}; };
static void tgen_xor(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_arith(s, a0, a1, a2, ARITH_XOR);
}
static void tgen_xori(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_arithi(s, a0, a1, a2, ARITH_XOR);
}
static const TCGOutOpBinary outop_xor = {
.base.static_constraint = C_O1_I2(r, r, rJ),
.out_rrr = tgen_xor,
.out_rri = tgen_xori,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -1419,9 +1437,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
OP_32_64(sub): OP_32_64(sub):
c = ARITH_SUB; c = ARITH_SUB;
goto gen_arith; goto gen_arith;
OP_32_64(xor):
c = ARITH_XOR;
goto gen_arith;
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
c = SHIFT_SLL; c = SHIFT_SLL;
do_shift32: do_shift32:
@ -1635,8 +1650,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_divu_i64: case INDEX_op_divu_i64:
case INDEX_op_sub_i32: case INDEX_op_sub_i32:
case INDEX_op_sub_i64: case INDEX_op_sub_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
case INDEX_op_shl_i64: case INDEX_op_shl_i64:
case INDEX_op_shr_i32: case INDEX_op_shr_i32:

4
tcg/tcg.c
View file

@ -1009,6 +1009,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or), OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc), OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
OUTOP(INDEX_op_xor_i32, TCGOutOpBinary, outop_xor),
OUTOP(INDEX_op_xor_i64, TCGOutOpBinary, outop_xor),
}; };
#undef OUTOP #undef OUTOP
@ -5440,6 +5442,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_andc: case INDEX_op_andc:
case INDEX_op_or: case INDEX_op_or:
case INDEX_op_orc: case INDEX_op_orc:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
{ {
const TCGOutOpBinary *out = const TCGOutOpBinary *out =
container_of(all_outop[op->opc], TCGOutOpBinary, base); container_of(all_outop[op->opc], TCGOutOpBinary, base);

14
tcg/tci/tcg-target.c.inc
View file

@ -101,8 +101,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_nand_i64: case INDEX_op_nand_i64:
case INDEX_op_nor_i32: case INDEX_op_nor_i32:
case INDEX_op_nor_i64: case INDEX_op_nor_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
case INDEX_op_shl_i64: case INDEX_op_shl_i64:
case INDEX_op_shr_i32: case INDEX_op_shr_i32:
@ -686,6 +684,17 @@ static const TCGOutOpBinary outop_orc = {
.out_rrr = tgen_orc, .out_rrr = tgen_orc,
}; };
static void tgen_xor(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_op_rrr(s, glue(INDEX_op_xor_i,TCG_TARGET_REG_BITS), a0, a1, a2);
}
static const TCGOutOpBinary outop_xor = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_xor,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -730,7 +739,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
CASE_32_64(sub) CASE_32_64(sub)
CASE_32_64(mul) CASE_32_64(mul)
CASE_32_64(xor)
CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */ CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */
CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */ CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */
CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */ CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */