motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-07 09:43:56 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: pmu: Rename the counters extension to pmu

Browse source 
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.

Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as well.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-4-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Atish Patra 2022-06-20 16:15:53 -07:00 • committed by Alistair Francis
parent a5a92fd6ef
commit d3be1299fb
3 changed files with 5 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

4
target/riscv/csr.c
View file

@ -74,8 +74,8 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index;
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
if (!cpu->cfg.ext_pmu) {
/* The PMU extension is not enabled */
return RISCV_EXCP_ILLEGAL_INST;
}