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i386/cpu: Extract a common fucntion to setup value of MSR_CORE_THREAD_COUNT
There are duplicated code to setup the value of MSR_CORE_THREAD_COUNT. Extract a common function for it. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20241219110125.1266461-2-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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5 changed files with 16 additions and 8 deletions
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@ -309,3 +309,14 @@ void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
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errp);
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errp);
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qapi_free_GuestPanicInformation(panic_info);
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qapi_free_GuestPanicInformation(panic_info);
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}
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}
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uint64_t cpu_x86_get_msr_core_thread_count(X86CPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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uint64_t val;
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val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
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val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
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return val;
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}
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@ -2413,6 +2413,8 @@ static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
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cs->halted = 0;
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cs->halted = 0;
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}
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}
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uint64_t cpu_x86_get_msr_core_thread_count(X86CPU *cpu);
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int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
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int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
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target_ulong *base, unsigned int *limit,
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target_ulong *base, unsigned int *limit,
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unsigned int *flags);
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unsigned int *flags);
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@ -765,8 +765,7 @@ void simulate_rdmsr(CPUX86State *env)
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val = env->mtrr_deftype;
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val = env->mtrr_deftype;
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break;
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break;
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case MSR_CORE_THREAD_COUNT:
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case MSR_CORE_THREAD_COUNT:
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val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
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val = cpu_x86_get_msr_core_thread_count(cpu);
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val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
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break;
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break;
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default:
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default:
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/* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
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/* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
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@ -2614,10 +2614,7 @@ static bool kvm_rdmsr_core_thread_count(X86CPU *cpu,
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uint32_t msr,
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uint32_t msr,
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uint64_t *val)
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uint64_t *val)
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{
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{
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CPUState *cs = CPU(cpu);
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*val = cpu_x86_get_msr_core_thread_count(cpu);
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*val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
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*val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
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return true;
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return true;
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}
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}
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@ -468,8 +468,7 @@ void helper_rdmsr(CPUX86State *env)
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val = x86_cpu->ucode_rev;
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val = x86_cpu->ucode_rev;
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break;
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break;
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case MSR_CORE_THREAD_COUNT: {
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case MSR_CORE_THREAD_COUNT: {
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CPUState *cs = CPU(x86_cpu);
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val = cpu_x86_get_msr_core_thread_count(x86_cpu);
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val = (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16);
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break;
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break;
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}
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}
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case MSR_APIC_START ... MSR_APIC_END: {
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case MSR_APIC_START ... MSR_APIC_END: {
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