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hw/intc/arm_gicv3_its: Keep CTEs as a struct, not a raw uint64_t

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In the ITS, a CTE is an entry in the collection table, which contains
multiple fields. Currently the function get_cte() which reads one
entry from the device table returns a success/failure boolean and
passes back the raw 64-bit integer CTE value via a pointer argument.
We then extract fields from the CTE as we need them.

Create a real C struct with the same fields as the CTE, and
populate it in get_cte(), so that that function and update_cte()
are the only ones which need to care about the in-guest-memory
format of the CTE.

This brings get_cte()'s API into line with get_dte().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220201193207.2771604-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-02-01 19:31:58 +00:00
parent 22d62b08ba
commit d37cf49b11
1 changed files with 52 additions and 44 deletions
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96
hw/intc/arm_gicv3_its.c
View file

@ -52,6 +52,11 @@ typedef struct DTEntry {
uint64_t ittaddr; uint64_t ittaddr;
} DTEntry; } DTEntry;
typedef struct CTEntry {
bool valid;
uint32_t rdbase;
} CTEntry;
/* /*
* The ITS spec permits a range of CONSTRAINED UNPREDICTABLE options * The ITS spec permits a range of CONSTRAINED UNPREDICTABLE options
* if a command parameter is not correct. These include both "stall * if a command parameter is not correct. These include both "stall
@ -135,18 +140,32 @@ static uint64_t table_entry_addr(GICv3ITSState *s, TableDesc *td,
return (l2 & ((1ULL << 51) - 1)) + (idx % num_l2_entries) * td->entry_sz; return (l2 & ((1ULL << 51) - 1)) + (idx % num_l2_entries) * td->entry_sz;
} }
static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t *cte, /*
MemTxResult *res) * Read the Collection Table entry at index @icid. On success (including
* successfully determining that there is no valid CTE for this index),
* we return MEMTX_OK and populate the CTEntry struct @cte accordingly.
* If there is an error reading memory then we return the error code.
*/
static MemTxResult get_cte(GICv3ITSState *s, uint16_t icid, CTEntry *cte)
{ {
AddressSpace *as = &s->gicv3->dma_as; AddressSpace *as = &s->gicv3->dma_as;
uint64_t entry_addr = table_entry_addr(s, &s->ct, icid, res); MemTxResult res = MEMTX_OK;
uint64_t entry_addr = table_entry_addr(s, &s->ct, icid, &res);
uint64_t cteval;
if (entry_addr == -1) { if (entry_addr == -1) {
return false; /* not valid */ /* No L2 table entry, i.e. no valid CTE, or a memory error */
cte->valid = false;
return res;
} }
*cte = address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, res); cteval = address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, &res);
return FIELD_EX64(*cte, CTE, VALID); if (res != MEMTX_OK) {
return res;
}
cte->valid = FIELD_EX64(cteval, CTE, VALID);
cte->rdbase = FIELD_EX64(cteval, CTE, RDBASE);
return MEMTX_OK;
} }
static bool update_ite(GICv3ITSState *s, uint32_t eventid, const DTEntry *dte, static bool update_ite(GICv3ITSState *s, uint32_t eventid, const DTEntry *dte,
@ -248,10 +267,8 @@ static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid,
uint16_t icid = 0; uint16_t icid = 0;
uint32_t pIntid = 0; uint32_t pIntid = 0;
bool ite_valid = false; bool ite_valid = false;
uint64_t cte = 0;
bool cte_valid = false;
uint64_t rdbase;
DTEntry dte; DTEntry dte;
CTEntry cte;
if (devid >= s->dt.num_entries) { if (devid >= s->dt.num_entries) {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
@ -298,15 +315,13 @@ static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid,
return CMD_CONTINUE; return CMD_CONTINUE;
} }
cte_valid = get_cte(s, icid, &cte, &res); if (get_cte(s, icid, &cte) != MEMTX_OK) {
if (res != MEMTX_OK) {
return CMD_STALL; return CMD_STALL;
} }
if (!cte_valid) { if (!cte.valid) {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid command attributes: " "%s: invalid command attributes: invalid CTE\n",
"invalid cte: %"PRIx64"\n", __func__);
__func__, cte);
return CMD_CONTINUE; return CMD_CONTINUE;
} }
@ -314,16 +329,14 @@ static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid,
* Current implementation only supports rdbase == procnum * Current implementation only supports rdbase == procnum
* Hence rdbase physical address is ignored * Hence rdbase physical address is ignored
*/ */
rdbase = FIELD_EX64(cte, CTE, RDBASE); if (cte.rdbase >= s->gicv3->num_cpu) {
if (rdbase >= s->gicv3->num_cpu) {
return CMD_CONTINUE; return CMD_CONTINUE;
} }
if ((cmd == CLEAR) || (cmd == DISCARD)) { if ((cmd == CLEAR) || (cmd == DISCARD)) {
gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 0); gicv3_redist_process_lpi(&s->gicv3->cpu[cte.rdbase], pIntid, 0);
} else { } else {
gicv3_redist_process_lpi(&s->gicv3->cpu[rdbase], pIntid, 1); gicv3_redist_process_lpi(&s->gicv3->cpu[cte.rdbase], pIntid, 1);
} }
if (cmd == DISCARD) { if (cmd == DISCARD) {
@ -564,12 +577,11 @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt)
MemTxResult res = MEMTX_OK; MemTxResult res = MEMTX_OK;
uint32_t devid, eventid, intid; uint32_t devid, eventid, intid;
uint16_t old_icid, new_icid; uint16_t old_icid, new_icid;
uint64_t old_cte, new_cte; bool ite_valid;
uint64_t old_rdbase, new_rdbase;
bool ite_valid, cte_valid;
uint64_t num_eventids; uint64_t num_eventids;
IteEntry ite = {}; IteEntry ite = {};
DTEntry dte; DTEntry dte;
CTEntry old_cte, new_cte;
devid = FIELD_EX64(cmdpkt[0], MOVI_0, DEVICEID); devid = FIELD_EX64(cmdpkt[0], MOVI_0, DEVICEID);
eventid = FIELD_EX64(cmdpkt[1], MOVI_1, EVENTID); eventid = FIELD_EX64(cmdpkt[1], MOVI_1, EVENTID);
@ -627,50 +639,46 @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt)
return CMD_CONTINUE; return CMD_CONTINUE;
} }
cte_valid = get_cte(s, old_icid, &old_cte, &res); if (get_cte(s, old_icid, &old_cte) != MEMTX_OK) {
if (res != MEMTX_OK) {
return CMD_STALL; return CMD_STALL;
} }
if (!cte_valid) { if (!old_cte.valid) {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid command attributes: " "%s: invalid command attributes: "
"invalid cte: %"PRIx64"\n", "invalid CTE for old ICID 0x%x\n",
__func__, old_cte); __func__, old_icid);
return CMD_CONTINUE; return CMD_CONTINUE;
} }
cte_valid = get_cte(s, new_icid, &new_cte, &res); if (get_cte(s, new_icid, &new_cte) != MEMTX_OK) {
if (res != MEMTX_OK) {
return CMD_STALL; return CMD_STALL;
} }
if (!cte_valid) { if (!new_cte.valid) {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid command attributes: " "%s: invalid command attributes: "
"invalid cte: %"PRIx64"\n", "invalid CTE for new ICID 0x%x\n",
__func__, new_cte); __func__, new_icid);
return CMD_CONTINUE; return CMD_CONTINUE;
} }
old_rdbase = FIELD_EX64(old_cte, CTE, RDBASE); if (old_cte.rdbase >= s->gicv3->num_cpu) {
if (old_rdbase >= s->gicv3->num_cpu) {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"%s: CTE has invalid rdbase 0x%"PRIx64"\n", "%s: CTE has invalid rdbase 0x%x\n",
__func__, old_rdbase); __func__, old_cte.rdbase);
return CMD_CONTINUE; return CMD_CONTINUE;
} }
new_rdbase = FIELD_EX64(new_cte, CTE, RDBASE); if (new_cte.rdbase >= s->gicv3->num_cpu) {
if (new_rdbase >= s->gicv3->num_cpu) {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"%s: CTE has invalid rdbase 0x%"PRIx64"\n", "%s: CTE has invalid rdbase 0x%x\n",
__func__, new_rdbase); __func__, new_cte.rdbase);
return CMD_CONTINUE; return CMD_CONTINUE;
} }
if (old_rdbase != new_rdbase) { if (old_cte.rdbase != new_cte.rdbase) {
/* Move the LPI from the old redistributor to the new one */ /* Move the LPI from the old redistributor to the new one */
gicv3_redist_mov_lpi(&s->gicv3->cpu[old_rdbase], gicv3_redist_mov_lpi(&s->gicv3->cpu[old_cte.rdbase],
&s->gicv3->cpu[new_rdbase], &s->gicv3->cpu[new_cte.rdbase],
intid); intid);
} }