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hw/riscv: Add a new struct RISCVBootInfo

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Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241120153935.24706-3-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Jim Shu 2024-11-20 23:39:34 +08:00 • committed by Alistair Francis
parent b4132a9e62
commit d3592955af
8 changed files with 91 additions and 57 deletions
Download patch file Download diff file Expand all files Collapse all files

59
hw/riscv/boot.c
View file

@ -67,9 +67,15 @@ char *riscv_plic_hart_config_string(int hart_count)
return g_strjoinv(",", (char **)vals); return g_strjoinv(",", (char **)vals);
} }
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)
{
info->kernel_size = 0;
info->is_32bit = riscv_is_32bit(harts);
}
target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
target_ulong firmware_end_addr) { target_ulong firmware_end_addr) {
if (riscv_is_32bit(harts)) { if (info->is_32bit) {
return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
} else { } else {
return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
@ -175,7 +181,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
exit(1); exit(1);
} }
static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info)
{ {
const char *filename = machine->initrd_filename; const char *filename = machine->initrd_filename;
uint64_t mem_size = machine->ram_size; uint64_t mem_size = machine->ram_size;
@ -196,7 +202,7 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
* halfway into RAM, and for boards with 1GB of RAM or more we put * halfway into RAM, and for boards with 1GB of RAM or more we put
* the initrd at 512MB. * the initrd at 512MB.
*/ */
start = kernel_entry + MIN(mem_size / 2, 512 * MiB); start = info->image_low_addr + MIN(mem_size / 2, 512 * MiB);
size = load_ramdisk(filename, start, mem_size - start); size = load_ramdisk(filename, start, mem_size - start);
if (size == -1) { if (size == -1) {
@ -215,14 +221,14 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
} }
} }
target_ulong riscv_load_kernel(MachineState *machine, void riscv_load_kernel(MachineState *machine,
RISCVHartArrayState *harts, RISCVBootInfo *info,
target_ulong kernel_start_addr, target_ulong kernel_start_addr,
bool load_initrd, bool load_initrd,
symbol_fn_t sym_cb) symbol_fn_t sym_cb)
{ {
const char *kernel_filename = machine->kernel_filename; const char *kernel_filename = machine->kernel_filename;
uint64_t kernel_load_base, kernel_entry; ssize_t kernel_size;
void *fdt = machine->fdt; void *fdt = machine->fdt;
g_assert(kernel_filename != NULL); g_assert(kernel_filename != NULL);
@ -234,21 +240,28 @@ target_ulong riscv_load_kernel(MachineState *machine,
* the (expected) load address load address. This allows kernels to have * the (expected) load address load address. This allows kernels to have
* separate SBI and ELF entry points (used by FreeBSD, for example). * separate SBI and ELF entry points (used by FreeBSD, for example).
*/ */
if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, kernel_size = load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL,
NULL, &kernel_load_base, NULL, NULL, 0, &info->image_low_addr, &info->image_high_addr,
EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb);
kernel_entry = kernel_load_base; if (kernel_size > 0) {
info->kernel_size = kernel_size;
goto out; goto out;
} }
if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, kernel_size = load_uimage_as(kernel_filename, &info->image_low_addr,
NULL, NULL, NULL) > 0) { NULL, NULL, NULL, NULL, NULL);
if (kernel_size > 0) {
info->kernel_size = kernel_size;
info->image_high_addr = info->image_low_addr + kernel_size;
goto out; goto out;
} }
if (load_image_targphys_as(kernel_filename, kernel_start_addr, kernel_size = load_image_targphys_as(kernel_filename, kernel_start_addr,
current_machine->ram_size, NULL) > 0) { current_machine->ram_size, NULL);
kernel_entry = kernel_start_addr; if (kernel_size > 0) {
info->kernel_size = kernel_size;
info->image_low_addr = kernel_start_addr;
info->image_high_addr = info->image_low_addr + kernel_size;
goto out; goto out;
} }
@ -257,23 +270,21 @@ target_ulong riscv_load_kernel(MachineState *machine,
out: out:
/* /*
* For 32 bit CPUs 'kernel_entry' can be sign-extended by * For 32 bit CPUs 'image_low_addr' can be sign-extended by
* load_elf_ram_sym(). * load_elf_ram_sym().
*/ */
if (riscv_is_32bit(harts)) { if (info->is_32bit) {
kernel_entry = extract64(kernel_entry, 0, 32); info->image_low_addr = extract64(info->image_low_addr, 0, 32);
} }
if (load_initrd && machine->initrd_filename) { if (load_initrd && machine->initrd_filename) {
riscv_load_initrd(machine, kernel_entry); riscv_load_initrd(machine, info);
} }
if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
machine->kernel_cmdline); machine->kernel_cmdline);
} }
return kernel_entry;
} }
/* /*
@ -293,7 +304,7 @@ out:
* The FDT is fdt_packed() during the calculation. * The FDT is fdt_packed() during the calculation.
*/ */
uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
MachineState *ms, RISCVHartArrayState *harts) MachineState *ms, RISCVBootInfo *info)
{ {
int ret = fdt_pack(ms->fdt); int ret = fdt_pack(ms->fdt);
hwaddr dram_end, temp; hwaddr dram_end, temp;
@ -321,7 +332,7 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
* Thus, put it near to the end of dram in RV64, and put it near to the end * Thus, put it near to the end of dram in RV64, and put it near to the end
* of dram or 3GB whichever is lesser in RV32. * of dram or 3GB whichever is lesser in RV32.
*/ */
if (!riscv_is_32bit(harts)) { if (!info->is_32bit) {
temp = dram_end; temp = dram_end;
} else { } else {
temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;

11
hw/riscv/microchip_pfsoc.c
View file

@ -521,6 +521,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
uint64_t kernel_entry; uint64_t kernel_entry;
uint64_t fdt_load_addr; uint64_t fdt_load_addr;
DriveInfo *dinfo = drive_get(IF_SD, 0, 0); DriveInfo *dinfo = drive_get(IF_SD, 0, 0);
RISCVBootInfo boot_info;
/* Sanity check on RAM size */ /* Sanity check on RAM size */
if (machine->ram_size < mc->default_ram_size) { if (machine->ram_size < mc->default_ram_size) {
@ -615,17 +616,19 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
&firmware_load_addr, NULL); &firmware_load_addr, NULL);
riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
if (kernel_as_payload) { if (kernel_as_payload) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr); firmware_end_addr);
kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, riscv_load_kernel(machine, &boot_info, kernel_start_addr,
kernel_start_addr, true, NULL); true, NULL);
kernel_entry = boot_info.image_low_addr;
/* Compute the fdt load address in dram */ /* Compute the fdt load address in dram */
fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
memmap[MICROCHIP_PFSOC_DRAM_LO].size, memmap[MICROCHIP_PFSOC_DRAM_LO].size,
machine, &s->soc.u_cpus); machine, &boot_info);
riscv_load_fdt(fdt_load_addr, machine->fdt); riscv_load_fdt(fdt_load_addr, machine->fdt);
/* Load the reset vector */ /* Load the reset vector */

4
hw/riscv/opentitan.c
View file

@ -81,6 +81,7 @@ static void opentitan_machine_init(MachineState *machine)
OpenTitanState *s = OPENTITAN_MACHINE(machine); OpenTitanState *s = OPENTITAN_MACHINE(machine);
const MemMapEntry *memmap = ibex_memmap; const MemMapEntry *memmap = ibex_memmap;
MemoryRegion *sys_mem = get_system_memory(); MemoryRegion *sys_mem = get_system_memory();
RISCVBootInfo boot_info;
if (machine->ram_size != mc->default_ram_size) { if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size); char *sz = size_to_str(mc->default_ram_size);
@ -102,8 +103,9 @@ static void opentitan_machine_init(MachineState *machine)
riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL); riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL);
} }
riscv_boot_info_init(&boot_info, &s->soc.cpus);
if (machine->kernel_filename) { if (machine->kernel_filename) {
riscv_load_kernel(machine, &s->soc.cpus, riscv_load_kernel(machine, &boot_info,
memmap[IBEX_DEV_RAM].base, memmap[IBEX_DEV_RAM].base,
false, NULL); false, NULL);
} }

4
hw/riscv/sifive_e.c
View file

@ -78,6 +78,7 @@ static void sifive_e_machine_init(MachineState *machine)
SiFiveEState *s = RISCV_E_MACHINE(machine); SiFiveEState *s = RISCV_E_MACHINE(machine);
MemoryRegion *sys_mem = get_system_memory(); MemoryRegion *sys_mem = get_system_memory();
int i; int i;
RISCVBootInfo boot_info;
if (machine->ram_size != mc->default_ram_size) { if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size); char *sz = size_to_str(mc->default_ram_size);
@ -113,8 +114,9 @@ static void sifive_e_machine_init(MachineState *machine)
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
riscv_boot_info_init(&boot_info, &s->soc.cpus);
if (machine->kernel_filename) { if (machine->kernel_filename) {
riscv_load_kernel(machine, &s->soc.cpus, riscv_load_kernel(machine, &boot_info,
memmap[SIFIVE_E_DEV_DTIM].base, memmap[SIFIVE_E_DEV_DTIM].base,
false, NULL); false, NULL);
} }

12
hw/riscv/sifive_u.c
View file

@ -526,6 +526,7 @@ static void sifive_u_machine_init(MachineState *machine)
BlockBackend *blk; BlockBackend *blk;
DeviceState *flash_dev, *sd_dev, *card_dev; DeviceState *flash_dev, *sd_dev, *card_dev;
qemu_irq flash_cs, sd_cs; qemu_irq flash_cs, sd_cs;
RISCVBootInfo boot_info;
/* Initialize SoC */ /* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
@ -591,12 +592,13 @@ static void sifive_u_machine_init(MachineState *machine)
firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
&start_addr, NULL); &start_addr, NULL);
riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
if (machine->kernel_filename) { if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr); firmware_end_addr);
riscv_load_kernel(machine, &boot_info, kernel_start_addr,
kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, true, NULL);
kernel_start_addr, true, NULL); kernel_entry = boot_info.image_low_addr;
} else { } else {
/* /*
* If dynamic firmware is used, it doesn't know where is the next mode * If dynamic firmware is used, it doesn't know where is the next mode
@ -607,7 +609,7 @@ static void sifive_u_machine_init(MachineState *machine)
fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
memmap[SIFIVE_U_DEV_DRAM].size, memmap[SIFIVE_U_DEV_DRAM].size,
machine, &s->soc.u_cpus); machine, &boot_info);
riscv_load_fdt(fdt_load_addr, machine->fdt); riscv_load_fdt(fdt_load_addr, machine->fdt);
if (!riscv_is_32bit(&s->soc.u_cpus)) { if (!riscv_is_32bit(&s->soc.u_cpus)) {

10
hw/riscv/spike.c
View file

@ -206,6 +206,7 @@ static void spike_board_init(MachineState *machine)
char *soc_name; char *soc_name;
int i, base_hartid, hart_count; int i, base_hartid, hart_count;
bool htif_custom_base = false; bool htif_custom_base = false;
RISCVBootInfo boot_info;
/* Check socket count limit */ /* Check socket count limit */
if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
@ -300,13 +301,14 @@ static void spike_board_init(MachineState *machine)
create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);
/* Load kernel */ /* Load kernel */
riscv_boot_info_init(&boot_info, &s->soc[0]);
if (machine->kernel_filename) { if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr); firmware_end_addr);
kernel_entry = riscv_load_kernel(machine, &s->soc[0], riscv_load_kernel(machine, &boot_info, kernel_start_addr,
kernel_start_addr,
true, htif_symbol_callback); true, htif_symbol_callback);
kernel_entry = boot_info.image_low_addr;
} else { } else {
/* /*
* If dynamic firmware is used, it doesn't know where is the next mode * If dynamic firmware is used, it doesn't know where is the next mode
@ -317,7 +319,7 @@ static void spike_board_init(MachineState *machine)
fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
memmap[SPIKE_DRAM].size, memmap[SPIKE_DRAM].size,
machine, &s->soc[0]); machine, &boot_info);
riscv_load_fdt(fdt_load_addr, machine->fdt); riscv_load_fdt(fdt_load_addr, machine->fdt);
/* load the reset vector */ /* load the reset vector */

15
hw/riscv/virt.c
View file

@ -1434,6 +1434,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
uint64_t fdt_load_addr; uint64_t fdt_load_addr;
uint64_t kernel_entry = 0; uint64_t kernel_entry = 0;
BlockBackend *pflash_blk0; BlockBackend *pflash_blk0;
RISCVBootInfo boot_info;
/* /*
* An user provided dtb must include everything, including * An user provided dtb must include everything, including
@ -1482,17 +1483,19 @@ static void virt_machine_done(Notifier *notifier, void *data)
} }
} }
if (machine->kernel_filename && !kernel_entry) { riscv_boot_info_init(&boot_info, &s->soc[0]);
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine, &s->soc[0], if (machine->kernel_filename && !kernel_entry) {
kernel_start_addr, true, NULL); kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr);
riscv_load_kernel(machine, &boot_info, kernel_start_addr,
true, NULL);
kernel_entry = boot_info.image_low_addr;
} }
fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
memmap[VIRT_DRAM].size, memmap[VIRT_DRAM].size,
machine, &s->soc[0]); machine, &boot_info);
riscv_load_fdt(fdt_load_addr, machine->fdt); riscv_load_fdt(fdt_load_addr, machine->fdt);
/* load the reset vector */ /* load the reset vector */

21
include/hw/riscv/boot.h
View file

@ -27,11 +27,20 @@
#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin" #define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin"
#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin" #define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
typedef struct RISCVBootInfo {
ssize_t kernel_size;
hwaddr image_low_addr;
hwaddr image_high_addr;
bool is_32bit;
} RISCVBootInfo;
bool riscv_is_32bit(RISCVHartArrayState *harts); bool riscv_is_32bit(RISCVHartArrayState *harts);
char *riscv_plic_hart_config_string(int hart_count); char *riscv_plic_hart_config_string(int hart_count);
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);
target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
target_ulong firmware_end_addr); target_ulong firmware_end_addr);
target_ulong riscv_find_and_load_firmware(MachineState *machine, target_ulong riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware, const char *default_machine_firmware,
@ -43,13 +52,13 @@ char *riscv_find_firmware(const char *firmware_filename,
target_ulong riscv_load_firmware(const char *firmware_filename, target_ulong riscv_load_firmware(const char *firmware_filename,
hwaddr *firmware_load_addr, hwaddr *firmware_load_addr,
symbol_fn_t sym_cb); symbol_fn_t sym_cb);
target_ulong riscv_load_kernel(MachineState *machine, void riscv_load_kernel(MachineState *machine,
RISCVHartArrayState *harts, RISCVBootInfo *info,
target_ulong firmware_end_addr, target_ulong kernel_start_addr,
bool load_initrd, bool load_initrd,
symbol_fn_t sym_cb); symbol_fn_t sym_cb);
uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
MachineState *ms, RISCVHartArrayState *harts); MachineState *ms, RISCVBootInfo *info);
void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
hwaddr saddr, hwaddr saddr,