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target-arm: Clean up handling of AArch64 PSTATE

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The env->pstate field is a little odd since it doesn't strictly
speaking represent an architectural register. However it's convenient
for QEMU to use it to hold the various PSTATE architectural bits
in the same format the architecture specifies for SPSR registers
(since this is the same format the kernel uses for signal handlers
and the KVM register). Add some structure to how we deal with it:
 * document what env->pstate is
 * add some #defines for various bits in it
 * add helpers for reading/writing it taking account of caching
   of NZCV, and use them where appropriate
 * reset it on startup

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1385645602-18662-3-git-send-email-peter.maydell@linaro.org
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
This commit is contained in:
Peter Maydell 2013-12-17 19:42:30 +00:00
parent b197ebd410
commit d356312fdc
5 changed files with 78 additions and 20 deletions
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6
target-arm/cpu.c
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@ -89,6 +89,12 @@ static void arm_cpu_reset(CPUState *s)
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
/* 64 bit CPUs always start in 64 bit mode */
env->aarch64 = 1;
#if defined(CONFIG_USER_ONLY)
env->pstate = PSTATE_MODE_EL0t;
#else
env->pstate = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F
| PSTATE_MODE_EL1h;
#endif
}
#if defined(CONFIG_USER_ONLY)