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target/riscv: Convert RVXM insns to decodetree

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Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2019-02-13 07:53:48 -08:00
parent 771fbe156a
commit d2e2c1e406
4 changed files with 137 additions and 9 deletions
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16
target/riscv/translate.c
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@ -1841,11 +1841,18 @@ static void decode_RV32_64C(DisasContext *ctx)
EX_SH(1)
EX_SH(12)
#define REQUIRE_EXT(ctx, ext) do { \
if (!has_ext(ctx, ext)) { \
return false; \
} \
} while (0)
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
static void decode_RV32_64G(DisasContext *ctx)
{
@ -1867,15 +1874,6 @@ static void decode_RV32_64G(DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
case OPC_RISC_ARITH:
#if defined(TARGET_RISCV64)
case OPC_RISC_ARITH_W:
#endif
if (rd == 0) {
break; /* NOP */
}
gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2);
break;
case OPC_RISC_FP_LOAD:
gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
break;