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tcg: Convert orc to TCGOutOpBinary

Browse source 
At the same time, drop all backend support for immediate
operands, as we now transform orc to or during optimize.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-06 14:30:50 -08:00
parent 50e40ecd7a
commit d262ae6081
26 changed files with 104 additions and 118 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tcg/aarch64/tcg-target-has.h
View file

@ -19,7 +19,6 @@
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_nor_i32 0
@ -44,7 +43,6 @@
#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0 #define TCG_TARGET_HAS_nor_i64 0

24
tcg/aarch64/tcg-target.c.inc
View file

@ -2175,6 +2175,17 @@ static const TCGOutOpBinary outop_or = {
.out_rri = tgen_ori, .out_rri = tgen_ori,
}; };
static void tgen_orc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_insn(s, 3510, ORN, type, a0, a1, a2);
}
static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_orc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -2256,17 +2267,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1); tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
break; break;
case INDEX_op_orc_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
case INDEX_op_orc_i64:
if (c2) {
tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, ~a2);
} else {
tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2);
}
break;
case INDEX_op_xor_i32: case INDEX_op_xor_i32:
a2 = (int32_t)a2; a2 = (int32_t)a2;
/* FALLTHRU */ /* FALLTHRU */
@ -3025,8 +3025,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_xor_i32: case INDEX_op_xor_i32:
case INDEX_op_xor_i64: case INDEX_op_xor_i64:
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64: case INDEX_op_eqv_i64:
return C_O1_I2(r, r, rL); return C_O1_I2(r, r, rL);

1
tcg/arm/tcg-target-has.h
View file

@ -28,7 +28,6 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_nor_i32 0

4
tcg/arm/tcg-target.c.inc
View file

@ -1899,6 +1899,10 @@ static const TCGOutOpBinary outop_or = {
.out_rri = tgen_ori, .out_rri = tgen_ori,
}; };
static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_NotImplemented,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],

2
tcg/i386/tcg-target-has.h
View file

@ -31,7 +31,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_nor_i32 0
@ -56,7 +55,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_orc_i64 0
#define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0 #define TCG_TARGET_HAS_nor_i64 0

4
tcg/i386/tcg-target.c.inc
View file

@ -2653,6 +2653,10 @@ static const TCGOutOpBinary outop_or = {
.out_rri = tgen_ori, .out_rri = tgen_ori,
}; };
static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_NotImplemented,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],

1
tcg/loongarch64/tcg-target-con-set.h
View file

@ -23,7 +23,6 @@ C_O1_I1(r, r)
C_O1_I1(w, r) C_O1_I1(w, r)
C_O1_I1(w, w) C_O1_I1(w, w)
C_O1_I2(r, r, r) C_O1_I2(r, r, r)
C_O1_I2(r, r, rC)
C_O1_I2(r, r, ri) C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI) C_O1_I2(r, r, rI)
C_O1_I2(r, r, rJ) C_O1_I2(r, r, rJ)

1
tcg/loongarch64/tcg-target-con-str.h
View file

@ -23,7 +23,6 @@ REGS('w', ALL_VECTOR_REGS)
CONST('I', TCG_CT_CONST_S12) CONST('I', TCG_CT_CONST_S12)
CONST('J', TCG_CT_CONST_S32) CONST('J', TCG_CT_CONST_S32)
CONST('U', TCG_CT_CONST_U12) CONST('U', TCG_CT_CONST_U12)
CONST('C', TCG_CT_CONST_C12)
CONST('W', TCG_CT_CONST_WSZ) CONST('W', TCG_CT_CONST_WSZ)
CONST('M', TCG_CT_CONST_VCMP) CONST('M', TCG_CT_CONST_VCMP)
CONST('A', TCG_CT_CONST_VADD) CONST('A', TCG_CT_CONST_VADD)

2
tcg/loongarch64/tcg-target-has.h
View file

@ -25,7 +25,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_nor_i32 1
@ -46,7 +45,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_nor_i64 1

40
tcg/loongarch64/tcg-target.c.inc
View file

@ -176,10 +176,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define TCG_CT_CONST_S12 0x100 #define TCG_CT_CONST_S12 0x100
#define TCG_CT_CONST_S32 0x200 #define TCG_CT_CONST_S32 0x200
#define TCG_CT_CONST_U12 0x400 #define TCG_CT_CONST_U12 0x400
#define TCG_CT_CONST_C12 0x800 #define TCG_CT_CONST_WSZ 0x800
#define TCG_CT_CONST_WSZ 0x1000 #define TCG_CT_CONST_VCMP 0x1000
#define TCG_CT_CONST_VCMP 0x2000 #define TCG_CT_CONST_VADD 0x2000
#define TCG_CT_CONST_VADD 0x4000
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
@ -205,9 +204,6 @@ static bool tcg_target_const_match(int64_t val, int ct,
if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) {
return true; return true;
} }
if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) {
return true;
}
if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
return true; return true;
} }
@ -1350,6 +1346,17 @@ static const TCGOutOpBinary outop_or = {
.out_rri = tgen_ori, .out_rri = tgen_ori,
}; };
static void tgen_orc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_opc_orn(s, a0, a1, a2);
}
static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_orc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -1400,16 +1407,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
break; break;
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
if (c2) {
/* guaranteed to fit due to constraint */
tcg_out_opc_ori(s, a0, a1, ~a2);
} else {
tcg_out_opc_orn(s, a0, a1, a2);
}
break;
case INDEX_op_xor_i32: case INDEX_op_xor_i32:
case INDEX_op_xor_i64: case INDEX_op_xor_i64:
if (c2) { if (c2) {
@ -2286,15 +2283,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_ld_i64:
return C_O1_I1(r, r); return C_O1_I1(r, r);
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
/*
* LoongArch insns for these ops don't have reg-imm forms, but we
* can express using andi/ori if ~constant satisfies
* TCG_CT_CONST_U12.
*/
return C_O1_I2(r, r, rC);
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
case INDEX_op_shl_i64: case INDEX_op_shl_i64:
case INDEX_op_shr_i32: case INDEX_op_shr_i32:

2
tcg/mips/tcg-target-has.h
View file

@ -43,7 +43,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_rem_i32 1 #define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions) #define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions)
@ -62,7 +61,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_rem_i64 1 #define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_orc_i64 0
#define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_add2_i64 0

4
tcg/mips/tcg-target.c.inc
View file

@ -1730,6 +1730,10 @@ static const TCGOutOpBinary outop_or = {
.out_rri = tgen_ori, .out_rri = tgen_ori,
}; };
static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_NotImplemented,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],

2
tcg/ppc/tcg-target-has.h
View file

@ -23,7 +23,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1 #define TCG_TARGET_HAS_nand_i32 1
#define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_nor_i32 1
@ -49,7 +48,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 1 #define TCG_TARGET_HAS_nand_i64 1
#define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_nor_i64 1

22
tcg/ppc/tcg-target.c.inc
View file

@ -2972,6 +2972,17 @@ static const TCGOutOpBinary outop_or = {
.out_rri = tgen_ori, .out_rri = tgen_ori,
}; };
static void tgen_orc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out32(s, ORC | SAB(a1, a0, a2));
}
static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_orc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -3066,15 +3077,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out32(s, XOR | SAB(a1, a0, a2)); tcg_out32(s, XOR | SAB(a1, a0, a2));
} }
break; break;
case INDEX_op_orc_i32:
if (const_args[2]) {
tcg_out_ori32(s, args[0], args[1], ~args[2]);
break;
}
/* FALLTHRU */
case INDEX_op_orc_i64:
tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
break;
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
if (const_args[2]) { if (const_args[2]) {
tcg_out_xori32(s, args[0], args[1], ~args[2]); tcg_out_xori32(s, args[0], args[1], ~args[2]);
@ -4140,7 +4142,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
return C_O0_I2(r, r); return C_O0_I2(r, r);
case INDEX_op_xor_i32: case INDEX_op_xor_i32:
case INDEX_op_orc_i32:
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
case INDEX_op_shr_i32: case INDEX_op_shr_i32:
@ -4166,7 +4167,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_nor_i32: case INDEX_op_nor_i32:
case INDEX_op_muluh_i32: case INDEX_op_muluh_i32:
case INDEX_op_mulsh_i32: case INDEX_op_mulsh_i32:
case INDEX_op_orc_i64:
case INDEX_op_eqv_i64: case INDEX_op_eqv_i64:
case INDEX_op_nand_i64: case INDEX_op_nand_i64:
case INDEX_op_nor_i64: case INDEX_op_nor_i64:

2
tcg/riscv/tcg-target-has.h
View file

@ -25,7 +25,6 @@
#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_nor_i32 0
@ -45,7 +44,6 @@
#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_orc_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0 #define TCG_TARGET_HAS_nor_i64 0

22
tcg/riscv/tcg-target.c.inc
View file

@ -2031,6 +2031,18 @@ static const TCGOutOpBinary outop_or = {
.out_rri = tgen_ori, .out_rri = tgen_ori,
}; };
static void tgen_orc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_opc_reg(s, OPC_ORN, a0, a1, a2);
}
static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_zbb_rrr,
.out_rrr = tgen_orc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -2118,14 +2130,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
break; break;
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_ORI, a0, a1, ~a2);
} else {
tcg_out_opc_reg(s, OPC_ORN, a0, a1, a2);
}
break;
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64: case INDEX_op_eqv_i64:
if (c2) { if (c2) {
@ -2699,8 +2703,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_negsetcond_i64: case INDEX_op_negsetcond_i64:
return C_O1_I2(r, r, rI); return C_O1_I2(r, r, rI);
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64: case INDEX_op_eqv_i64:
return C_O1_I2(r, r, rJ); return C_O1_I2(r, r, rJ);

2
tcg/s390x/tcg-target-has.h
View file

@ -34,7 +34,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_not_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_orc_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_eqv_i32 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_eqv_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nand_i32 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_nand_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nor_i32 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_nor_i32 HAVE_FACILITY(MISC_INSN_EXT3)
@ -58,7 +57,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_not_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_orc_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_eqv_i64 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_eqv_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nand_i64 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_nand_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nor_i64 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_nor_i64 HAVE_FACILITY(MISC_INSN_EXT3)

36
tcg/s390x/tcg-target.c.inc
View file

@ -2267,6 +2267,22 @@ static const TCGOutOpBinary outop_or = {
.out_rri = tgen_ori_3, .out_rri = tgen_ori_3,
}; };
static void tgen_orc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
if (type == TCG_TYPE_I32) {
tcg_out_insn(s, RRFa, OCRK, a0, a1, a2);
} else {
tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2);
}
}
static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_misc3_rrr,
.out_rrr = tgen_orc,
};
# define OP_32_64(x) \ # define OP_32_64(x) \
case glue(glue(INDEX_op_,x),_i32): \ case glue(glue(INDEX_op_,x),_i32): \
@ -2347,15 +2363,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
break; break;
case INDEX_op_orc_i32:
a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
if (const_args[2]) {
tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
tgen_ori(s, a0, (uint32_t)~a2);
} else {
tcg_out_insn(s, RRFa, OCRK, a0, a1, a2);
}
break;
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
if (const_args[2]) { if (const_args[2]) {
@ -2585,15 +2592,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
} }
break; break;
case INDEX_op_orc_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
tgen_ori(s, a0, ~a2);
} else {
tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2);
}
break;
case INDEX_op_eqv_i64: case INDEX_op_eqv_i64:
a0 = args[0], a1 = args[1], a2 = args[2]; a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) { if (const_args[2]) {
@ -3292,10 +3290,8 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_xor_i64: case INDEX_op_xor_i64:
return C_O1_I2(r, r, rK); return C_O1_I2(r, r, rK);
case INDEX_op_orc_i32:
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
return C_O1_I2(r, r, ri); return C_O1_I2(r, r, ri);
case INDEX_op_orc_i64:
case INDEX_op_eqv_i64: case INDEX_op_eqv_i64:
return C_O1_I2(r, r, rNK); return C_O1_I2(r, r, rNK);

2
tcg/sparc64/tcg-target-has.h
View file

@ -20,7 +20,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_bswap16_i32 0 #define TCG_TARGET_HAS_bswap16_i32 0
#define TCG_TARGET_HAS_bswap32_i32 0 #define TCG_TARGET_HAS_bswap32_i32 0
#define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_nor_i32 0
@ -45,7 +44,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_bswap32_i64 0 #define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0 #define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0 #define TCG_TARGET_HAS_nor_i64 0

16
tcg/sparc64/tcg-target.c.inc
View file

@ -1351,6 +1351,17 @@ static const TCGOutOpBinary outop_or = {
.out_rri = tgen_ori, .out_rri = tgen_ori,
}; };
static void tgen_orc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_arith(s, a0, a1, a2, ARITH_ORN);
}
static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_orc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -1408,9 +1419,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
OP_32_64(sub): OP_32_64(sub):
c = ARITH_SUB; c = ARITH_SUB;
goto gen_arith; goto gen_arith;
OP_32_64(orc):
c = ARITH_ORN;
goto gen_arith;
OP_32_64(xor): OP_32_64(xor):
c = ARITH_XOR; c = ARITH_XOR;
goto gen_arith; goto gen_arith;
@ -1627,8 +1635,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_divu_i64: case INDEX_op_divu_i64:
case INDEX_op_sub_i32: case INDEX_op_sub_i32:
case INDEX_op_sub_i64: case INDEX_op_sub_i64:
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
case INDEX_op_xor_i32: case INDEX_op_xor_i32:
case INDEX_op_xor_i64: case INDEX_op_xor_i64:
case INDEX_op_shl_i32: case INDEX_op_shl_i32:

1
tcg/tcg-has.h
View file

@ -20,7 +20,6 @@
#define TCG_TARGET_HAS_bswap32_i64 0 #define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0 #define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_not_i64 0 #define TCG_TARGET_HAS_not_i64 0
#define TCG_TARGET_HAS_orc_i64 0
#define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0 #define TCG_TARGET_HAS_nor_i64 0

4
tcg/tcg-op.c
View file

@ -710,7 +710,7 @@ void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{ {
if (TCG_TARGET_HAS_orc_i32) { if (tcg_op_supported(INDEX_op_orc_i32, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
} else { } else {
TCGv_i32 t0 = tcg_temp_ebb_new_i32(); TCGv_i32 t0 = tcg_temp_ebb_new_i32();
@ -2318,7 +2318,7 @@ void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
if (TCG_TARGET_REG_BITS == 32) { if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
} else if (TCG_TARGET_HAS_orc_i64) { } else if (tcg_op_supported(INDEX_op_orc_i64, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
} else { } else {
TCGv_i64 t0 = tcg_temp_ebb_new_i64(); TCGv_i64 t0 = tcg_temp_ebb_new_i64();

8
tcg/tcg.c
View file

@ -1008,6 +1008,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and), OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and),
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or), OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
OUTOP(INDEX_op_orc_i32, TCGOutOpBinary, outop_orc),
OUTOP(INDEX_op_orc_i64, TCGOutOpBinary, outop_orc),
}; };
#undef OUTOP #undef OUTOP
@ -2271,8 +2273,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_bswap32_i32; return TCG_TARGET_HAS_bswap32_i32;
case INDEX_op_not_i32: case INDEX_op_not_i32:
return TCG_TARGET_HAS_not_i32; return TCG_TARGET_HAS_not_i32;
case INDEX_op_orc_i32:
return TCG_TARGET_HAS_orc_i32;
case INDEX_op_eqv_i32: case INDEX_op_eqv_i32:
return TCG_TARGET_HAS_eqv_i32; return TCG_TARGET_HAS_eqv_i32;
case INDEX_op_nand_i32: case INDEX_op_nand_i32:
@ -2345,8 +2345,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_bswap64_i64; return TCG_TARGET_HAS_bswap64_i64;
case INDEX_op_not_i64: case INDEX_op_not_i64:
return TCG_TARGET_HAS_not_i64; return TCG_TARGET_HAS_not_i64;
case INDEX_op_orc_i64:
return TCG_TARGET_HAS_orc_i64;
case INDEX_op_eqv_i64: case INDEX_op_eqv_i64:
return TCG_TARGET_HAS_eqv_i64; return TCG_TARGET_HAS_eqv_i64;
case INDEX_op_nand_i64: case INDEX_op_nand_i64:
@ -5442,6 +5440,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_and: case INDEX_op_and:
case INDEX_op_andc: case INDEX_op_andc:
case INDEX_op_or: case INDEX_op_or:
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
{ {
const TCGOutOpBinary *out = const TCGOutOpBinary *out =
container_of(all_outop[op->opc], TCGOutOpBinary, base); container_of(all_outop[op->opc], TCGOutOpBinary, base);

2
tcg/tci.c
View file

@ -551,12 +551,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2); tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] & ~regs[r2]; regs[r0] = regs[r1] & ~regs[r2];
break; break;
#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64
CASE_32_64(orc) CASE_32_64(orc)
tci_args_rrr(insn, &r0, &r1, &r2); tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] | ~regs[r2]; regs[r0] = regs[r1] | ~regs[r2];
break; break;
#endif
#if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64 #if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64
CASE_32_64(eqv) CASE_32_64(eqv)
tci_args_rrr(insn, &r0, &r1, &r2); tci_args_rrr(insn, &r0, &r1, &r2);

2
tcg/tci/tcg-target-has.h
View file

@ -19,7 +19,6 @@
#define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctz_i32 1
#define TCG_TARGET_HAS_ctpop_i32 1 #define TCG_TARGET_HAS_ctpop_i32 1
#define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_negsetcond_i32 0
#define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muls2_i32 1
@ -42,7 +41,6 @@
#define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_ctz_i64 1
#define TCG_TARGET_HAS_ctpop_i64 1 #define TCG_TARGET_HAS_ctpop_i64 1
#define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_negsetcond_i64 0 #define TCG_TARGET_HAS_negsetcond_i64 0
#define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_muls2_i64 1

14
tcg/tci/tcg-target.c.inc
View file

@ -101,8 +101,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_nand_i64: case INDEX_op_nand_i64:
case INDEX_op_nor_i32: case INDEX_op_nor_i32:
case INDEX_op_nor_i64: case INDEX_op_nor_i64:
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
case INDEX_op_xor_i32: case INDEX_op_xor_i32:
case INDEX_op_xor_i64: case INDEX_op_xor_i64:
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
@ -677,6 +675,17 @@ static const TCGOutOpBinary outop_or = {
.out_rrr = tgen_or, .out_rrr = tgen_or,
}; };
static void tgen_orc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_op_rrr(s, glue(INDEX_op_orc_i,TCG_TARGET_REG_BITS), a0, a1, a2);
}
static const TCGOutOpBinary outop_orc = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_orc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS], const TCGArg args[TCG_MAX_OP_ARGS],
@ -722,7 +731,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
CASE_32_64(sub) CASE_32_64(sub)
CASE_32_64(mul) CASE_32_64(mul)
CASE_32_64(xor) CASE_32_64(xor)
CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */
CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */ CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */
CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */ CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */
CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */ CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */