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target/riscv: Implement AIA xiselect and xireg CSRs

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The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-15-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2022-02-04 23:16:50 +05:30 • committed by Alistair Francis
parent c7de92b4e8
commit d1ceff405a
3 changed files with 187 additions and 0 deletions
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7
target/riscv/cpu.h
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@ -196,6 +196,10 @@ struct CPURISCVState {
uint8_t miprio[64];
uint8_t siprio[64];
/* AIA CSRs */
target_ulong miselect;
target_ulong siselect;
/* Hypervisor CSRs */
target_ulong hstatus;
target_ulong hedeleg;
@ -229,6 +233,9 @@ struct CPURISCVState {
target_ulong vstval;
target_ulong vsatp;
/* AIA VS-mode CSRs */
target_ulong vsiselect;
target_ulong mtval2;
target_ulong mtinst;