motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-18 23:52:14 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/arm: Update arm_phys_excp_target_el for TGE

Browse source 
The TGE bit routes all asynchronous exceptions to EL2.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-07 14:04:26 +00:00 • committed by Peter Maydell
parent 85d0dc9fa2
commit d1b31428fd
1 changed files with 6 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
target/arm/helper.c
View file

@ -8446,6 +8446,12 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
break; break;
}; };
/*
* For these purposes, TGE and AMO/IMO/FMO both force the
* interrupt to EL2. Fold TGE into the bit extracted above.
*/
hcr |= (hcr_el2 & HCR_TGE) != 0;
/* Perform a table-lookup for the target EL given the current state */ /* Perform a table-lookup for the target EL given the current state */
target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];