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target/arm: generate xml description of our SVE registers

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We also expose a the helpers to read/write the the registers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Richard Henderson <richard.henderson@linaro.org>

Message-Id: <20200316172155.971-19-alex.bennee@linaro.org>
This commit is contained in:
Alex Bennée 2020-03-16 17:21:45 +00:00
parent 7b6a2198e7
commit d12379c598
3 changed files with 261 additions and 5 deletions
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134
target/arm/gdbstub.c
View file

@ -171,12 +171,146 @@ int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
return cpu->dyn_sysreg_xml.num;
}
struct TypeSize {
const char *gdb_type;
int size;
const char sz, suffix;
};
static const struct TypeSize vec_lanes[] = {
/* quads */
{ "uint128", 128, 'q', 'u' },
{ "int128", 128, 'q', 's' },
/* 64 bit */
{ "uint64", 64, 'd', 'u' },
{ "int64", 64, 'd', 's' },
{ "ieee_double", 64, 'd', 'f' },
/* 32 bit */
{ "uint32", 32, 's', 'u' },
{ "int32", 32, 's', 's' },
{ "ieee_single", 32, 's', 'f' },
/* 16 bit */
{ "uint16", 16, 'h', 'u' },
{ "int16", 16, 'h', 's' },
{ "ieee_half", 16, 'h', 'f' },
/* bytes */
{ "uint8", 8, 'b', 'u' },
{ "int8", 8, 'b', 's' },
};
int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
{
ARMCPU *cpu = ARM_CPU(cs);
GString *s = g_string_new(NULL);
DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
g_autoptr(GString) ts = g_string_new("");
int i, bits, reg_width = (cpu->sve_max_vq * 128);
info->num = 0;
g_string_printf(s, "<?xml version=\"1.0\"?>");
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
g_string_append_printf(s, "<feature name=\"org.qemu.gdb.aarch64.sve\">");
/* First define types and totals in a whole VL */
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
int count = reg_width / vec_lanes[i].size;
g_string_printf(ts, "vq%d%c%c", count,
vec_lanes[i].sz, vec_lanes[i].suffix);
g_string_append_printf(s,
"<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
ts->str, vec_lanes[i].gdb_type, count);
}
/*
* Now define a union for each size group containing unsigned and
* signed and potentially float versions of each size from 128 to
* 8 bits.
*/
for (bits = 128; bits >= 8; bits /= 2) {
int count = reg_width / bits;
g_string_append_printf(s, "<union id=\"vq%dn\">", count);
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
if (vec_lanes[i].size == bits) {
g_string_append_printf(s, "<field name=\"%c\" type=\"vq%d%c%c\"/>",
vec_lanes[i].suffix,
count,
vec_lanes[i].sz, vec_lanes[i].suffix);
}
}
g_string_append(s, "</union>");
}
/* And now the final union of unions */
g_string_append(s, "<union id=\"vq\">");
for (bits = 128; bits >= 8; bits /= 2) {
int count = reg_width / bits;
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
if (vec_lanes[i].size == bits) {
g_string_append_printf(s, "<field name=\"%c\" type=\"vq%dn\"/>",
vec_lanes[i].sz, count);
break;
}
}
}
g_string_append(s, "</union>");
/* Then define each register in parts for each vq */
for (i = 0; i < 32; i++) {
g_string_append_printf(s,
"<reg name=\"z%d\" bitsize=\"%d\""
" regnum=\"%d\" group=\"vector\""
" type=\"vq\"/>",
i, reg_width, base_reg++);
info->num++;
}
/* fpscr & status registers */
g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
" regnum=\"%d\" group=\"float\""
" type=\"int\"/>", base_reg++);
g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
" regnum=\"%d\" group=\"float\""
" type=\"int\"/>", base_reg++);
info->num += 2;
/*
* Predicate registers aren't so big they are worth splitting up
* but we do need to define a type to hold the array of quad
* references.
*/
g_string_append_printf(s,
"<vector id=\"vqp\" type=\"uint16\" count=\"%d\"/>",
cpu->sve_max_vq);
for (i = 0; i < 16; i++) {
g_string_append_printf(s,
"<reg name=\"p%d\" bitsize=\"%d\""
" regnum=\"%d\" group=\"vector\""
" type=\"vqp\"/>",
i, cpu->sve_max_vq * 16, base_reg++);
info->num++;
}
g_string_append_printf(s,
"<reg name=\"ffr\" bitsize=\"%d\""
" regnum=\"%d\" group=\"vector\""
" type=\"vqp\"/>",
cpu->sve_max_vq * 16, base_reg++);
g_string_append_printf(s,
"<reg name=\"vg\" bitsize=\"64\""
" regnum=\"%d\" group=\"vector\""
" type=\"uint32\"/>",
base_reg++);
info->num += 2;
g_string_append_printf(s, "</feature>");
cpu->dyn_svereg_xml.desc = g_string_free(s, false);
return cpu->dyn_svereg_xml.num;
}
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
{
ARMCPU *cpu = ARM_CPU(cs);
if (strcmp(xmlname, "system-registers.xml") == 0) {
return cpu->dyn_sysreg_xml.desc;
} else if (strcmp(xmlname, "sve-registers.xml") == 0) {
return cpu->dyn_svereg_xml.desc;
}
return NULL;
}