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hw/block: replace TABs with space
Bring the block files in line with the QEMU coding style, with spaces for indentation. This patch partially resolves the issue 371. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/371 Signed-off-by: Yeqi Fu <fufuyqqqqqq@gmail.com> Message-Id: <20230314095001.13801-1-fufuyqqqqqq@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Yeqi Fu
Thomas Huth
parent
0030b244a7
commit
d091b5b442
5 changed files with 248 additions and 248 deletions
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@ -35,10 +35,10 @@
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#include "qom/object.h"
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/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
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#define PAGE_SHIFT 11
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#define PAGE_SHIFT 11
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/* Fixed */
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#define BLOCK_SHIFT (PAGE_SHIFT + 6)
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#define BLOCK_SHIFT (PAGE_SHIFT + 6)
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#define TYPE_ONE_NAND "onenand"
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OBJECT_DECLARE_SIMPLE_TYPE(OneNANDState, ONE_NAND)
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@ -408,23 +408,23 @@ static void onenand_command(OneNANDState *s)
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int b;
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int sec;
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void *buf;
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#define SETADDR(block, page) \
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sec = (s->addr[page] & 3) + \
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((((s->addr[page] >> 2) & 0x3f) + \
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(((s->addr[block] & 0xfff) | \
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(s->addr[block] >> 15 ? \
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s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9));
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#define SETBUF_M() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \
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#define SETADDR(block, page) \
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sec = (s->addr[page] & 3) + \
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((((s->addr[page] >> 2) & 0x3f) + \
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(((s->addr[block] & 0xfff) | \
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(s->addr[block] >> 15 ? s->density_mask : 0)) \
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<< 6)) \
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<< (PAGE_SHIFT - 9));
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#define SETBUF_M() \
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buf = (s->bufaddr & 8) ? s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \
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buf += (s->bufaddr & 3) << 9;
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#define SETBUF_S() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
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#define SETBUF_S() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
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buf += (s->bufaddr & 3) << 4;
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switch (s->command) {
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case 0x00: /* Load single/multiple sector data unit into buffer */
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case 0x00: /* Load single/multiple sector data unit into buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_M()
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@ -443,7 +443,7 @@ static void onenand_command(OneNANDState *s)
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD;
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break;
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case 0x13: /* Load single/multiple spare sector into buffer */
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case 0x13: /* Load single/multiple spare sector into buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_S()
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@ -456,7 +456,7 @@ static void onenand_command(OneNANDState *s)
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD;
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break;
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case 0x80: /* Program single/multiple sector data unit from buffer */
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case 0x80: /* Program single/multiple sector data unit from buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_M()
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@ -475,7 +475,7 @@ static void onenand_command(OneNANDState *s)
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG;
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break;
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case 0x1a: /* Program single/multiple spare area sector from buffer */
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case 0x1a: /* Program single/multiple spare area sector from buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_S()
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@ -488,7 +488,7 @@ static void onenand_command(OneNANDState *s)
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG;
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break;
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case 0x1b: /* Copy-back program */
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case 0x1b: /* Copy-back program */
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SETBUF_S()
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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@ -504,7 +504,7 @@ static void onenand_command(OneNANDState *s)
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s->intstatus |= ONEN_INT | ONEN_INT_PROG;
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break;
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case 0x23: /* Unlock NAND array block(s) */
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case 0x23: /* Unlock NAND array block(s) */
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s->intstatus |= ONEN_INT;
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/* XXX the previous (?) area should be locked automatically */
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@ -519,7 +519,7 @@ static void onenand_command(OneNANDState *s)
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s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED;
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}
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break;
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case 0x27: /* Unlock All NAND array blocks */
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case 0x27: /* Unlock All NAND array blocks */
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s->intstatus |= ONEN_INT;
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for (b = 0; b < s->blocks; b ++) {
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@ -530,7 +530,7 @@ static void onenand_command(OneNANDState *s)
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}
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break;
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case 0x2a: /* Lock NAND array block(s) */
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case 0x2a: /* Lock NAND array block(s) */
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s->intstatus |= ONEN_INT;
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for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
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@ -544,7 +544,7 @@ static void onenand_command(OneNANDState *s)
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s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED;
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}
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break;
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case 0x2c: /* Lock-tight NAND array block(s) */
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case 0x2c: /* Lock-tight NAND array block(s) */
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s->intstatus |= ONEN_INT;
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for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
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@ -559,13 +559,13 @@ static void onenand_command(OneNANDState *s)
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}
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break;
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case 0x71: /* Erase-Verify-Read */
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case 0x71: /* Erase-Verify-Read */
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s->intstatus |= ONEN_INT;
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break;
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case 0x95: /* Multi-block erase */
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case 0x95: /* Multi-block erase */
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qemu_irq_pulse(s->intr);
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/* Fall through. */
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case 0x94: /* Block erase */
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case 0x94: /* Block erase */
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sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
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(s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0))
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<< (BLOCK_SHIFT - 9);
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@ -574,20 +574,20 @@ static void onenand_command(OneNANDState *s)
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s->intstatus |= ONEN_INT | ONEN_INT_ERASE;
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break;
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case 0xb0: /* Erase suspend */
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case 0xb0: /* Erase suspend */
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break;
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case 0x30: /* Erase resume */
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case 0x30: /* Erase resume */
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s->intstatus |= ONEN_INT | ONEN_INT_ERASE;
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break;
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case 0xf0: /* Reset NAND Flash core */
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case 0xf0: /* Reset NAND Flash core */
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onenand_reset(s, 0);
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break;
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case 0xf3: /* Reset OneNAND */
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case 0xf3: /* Reset OneNAND */
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onenand_reset(s, 0);
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break;
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case 0x65: /* OTP Access */
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case 0x65: /* OTP Access */
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s->intstatus |= ONEN_INT;
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s->blk_cur = NULL;
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s->current = s->otp;
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@ -616,52 +616,52 @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
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case 0x0000 ... 0xbffe:
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return lduw_le_p(s->boot[0] + addr);
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case 0xf000: /* Manufacturer ID */
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case 0xf000: /* Manufacturer ID */
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return s->id.man;
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case 0xf001: /* Device ID */
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case 0xf001: /* Device ID */
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return s->id.dev;
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case 0xf002: /* Version ID */
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case 0xf002: /* Version ID */
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return s->id.ver;
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/* TODO: get the following values from a real chip! */
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case 0xf003: /* Data Buffer size */
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case 0xf003: /* Data Buffer size */
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return 1 << PAGE_SHIFT;
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case 0xf004: /* Boot Buffer size */
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case 0xf004: /* Boot Buffer size */
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return 0x200;
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case 0xf005: /* Amount of buffers */
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case 0xf005: /* Amount of buffers */
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return 1 | (2 << 8);
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case 0xf006: /* Technology */
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case 0xf006: /* Technology */
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return 0;
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case 0xf100 ... 0xf107: /* Start addresses */
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case 0xf100 ... 0xf107: /* Start addresses */
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return s->addr[offset - 0xf100];
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case 0xf200: /* Start buffer */
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case 0xf200: /* Start buffer */
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return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10)));
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case 0xf220: /* Command */
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case 0xf220: /* Command */
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return s->command;
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case 0xf221: /* System Configuration 1 */
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case 0xf221: /* System Configuration 1 */
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return s->config[0] & 0xffe0;
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case 0xf222: /* System Configuration 2 */
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case 0xf222: /* System Configuration 2 */
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return s->config[1];
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case 0xf240: /* Controller Status */
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case 0xf240: /* Controller Status */
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return s->status;
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case 0xf241: /* Interrupt */
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case 0xf241: /* Interrupt */
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return s->intstatus;
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case 0xf24c: /* Unlock Start Block Address */
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case 0xf24c: /* Unlock Start Block Address */
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return s->unladdr[0];
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case 0xf24d: /* Unlock End Block Address */
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case 0xf24d: /* Unlock End Block Address */
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return s->unladdr[1];
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case 0xf24e: /* Write Protection Status */
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case 0xf24e: /* Write Protection Status */
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return s->wpstatus;
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case 0xff00: /* ECC Status */
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case 0xff00: /* ECC Status */
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return 0x00;
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case 0xff01: /* ECC Result of main area data */
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case 0xff02: /* ECC Result of spare area data */
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case 0xff03: /* ECC Result of main area data */
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case 0xff04: /* ECC Result of spare area data */
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case 0xff01: /* ECC Result of main area data */
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case 0xff02: /* ECC Result of spare area data */
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case 0xff03: /* ECC Result of main area data */
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case 0xff04: /* ECC Result of spare area data */
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qemu_log_mask(LOG_UNIMP,
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"onenand: ECC result registers unimplemented\n");
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return 0x0000;
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@ -696,15 +696,15 @@ static void onenand_write(void *opaque, hwaddr addr,
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}
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switch (value) {
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case 0x00f0: /* Reset OneNAND */
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case 0x00f0: /* Reset OneNAND */
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onenand_reset(s, 0);
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break;
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case 0x00e0: /* Load Data into Buffer */
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case 0x00e0: /* Load Data into Buffer */
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s->cycle = 1;
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break;
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case 0x0090: /* Read Identification Data */
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case 0x0090: /* Read Identification Data */
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memset(s->boot[0], 0, 3 << s->shift);
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s->boot[0][0 << s->shift] = s->id.man & 0xff;
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s->boot[0][1 << s->shift] = s->id.dev & 0xff;
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@ -718,11 +718,11 @@ static void onenand_write(void *opaque, hwaddr addr,
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}
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break;
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case 0xf100 ... 0xf107: /* Start addresses */
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case 0xf100 ... 0xf107: /* Start addresses */
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s->addr[offset - 0xf100] = value;
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break;
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case 0xf200: /* Start buffer */
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case 0xf200: /* Start buffer */
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s->bufaddr = (value >> 8) & 0xf;
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if (PAGE_SHIFT == 11)
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s->count = (value & 3) ?: 4;
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@ -730,36 +730,36 @@ static void onenand_write(void *opaque, hwaddr addr,
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s->count = (value & 1) ?: 2;
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break;
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case 0xf220: /* Command */
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case 0xf220: /* Command */
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if (s->intstatus & (1 << 15))
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break;
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s->command = value;
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onenand_command(s);
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break;
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case 0xf221: /* System Configuration 1 */
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case 0xf221: /* System Configuration 1 */
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s->config[0] = value;
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onenand_intr_update(s);
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qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1);
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break;
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case 0xf222: /* System Configuration 2 */
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case 0xf222: /* System Configuration 2 */
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s->config[1] = value;
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break;
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case 0xf241: /* Interrupt */
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case 0xf241: /* Interrupt */
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s->intstatus &= value;
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if ((1 << 15) & ~s->intstatus)
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s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE |
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ONEN_ERR_PROG | ONEN_ERR_LOAD);
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onenand_intr_update(s);
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break;
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case 0xf24c: /* Unlock Start Block Address */
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case 0xf24c: /* Unlock Start Block Address */
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s->unladdr[0] = value & (s->blocks - 1);
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/* For some reason we have to set the end address to by default
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* be same as start because the software forgets to write anything
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* in there. */
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s->unladdr[1] = value & (s->blocks - 1);
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break;
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case 0xf24d: /* Unlock End Block Address */
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case 0xf24d: /* Unlock End Block Address */
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s->unladdr[1] = value & (s->blocks - 1);
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break;
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