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hw/block: replace TABs with space
Bring the block files in line with the QEMU coding style, with spaces for indentation. This patch partially resolves the issue 371. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/371 Signed-off-by: Yeqi Fu <fufuyqqqqqq@gmail.com> Message-Id: <20230314095001.13801-1-fufuyqqqqqq@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Yeqi Fu
Thomas Huth
parent
0030b244a7
commit
d091b5b442
5 changed files with 248 additions and 248 deletions
208
hw/block/nand.c
208
hw/block/nand.c
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@ -30,33 +30,33 @@
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#include "qemu/module.h"
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#include "qom/object.h"
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# define NAND_CMD_READ0 0x00
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# define NAND_CMD_READ1 0x01
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# define NAND_CMD_READ2 0x50
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# define NAND_CMD_LPREAD2 0x30
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# define NAND_CMD_NOSERIALREAD2 0x35
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# define NAND_CMD_RANDOMREAD1 0x05
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# define NAND_CMD_RANDOMREAD2 0xe0
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# define NAND_CMD_READID 0x90
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# define NAND_CMD_RESET 0xff
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# define NAND_CMD_PAGEPROGRAM1 0x80
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# define NAND_CMD_PAGEPROGRAM2 0x10
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# define NAND_CMD_CACHEPROGRAM2 0x15
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# define NAND_CMD_BLOCKERASE1 0x60
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# define NAND_CMD_BLOCKERASE2 0xd0
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# define NAND_CMD_READSTATUS 0x70
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# define NAND_CMD_COPYBACKPRG1 0x85
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# define NAND_CMD_READ0 0x00
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# define NAND_CMD_READ1 0x01
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# define NAND_CMD_READ2 0x50
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# define NAND_CMD_LPREAD2 0x30
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# define NAND_CMD_NOSERIALREAD2 0x35
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# define NAND_CMD_RANDOMREAD1 0x05
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# define NAND_CMD_RANDOMREAD2 0xe0
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# define NAND_CMD_READID 0x90
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# define NAND_CMD_RESET 0xff
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# define NAND_CMD_PAGEPROGRAM1 0x80
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# define NAND_CMD_PAGEPROGRAM2 0x10
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# define NAND_CMD_CACHEPROGRAM2 0x15
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# define NAND_CMD_BLOCKERASE1 0x60
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# define NAND_CMD_BLOCKERASE2 0xd0
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# define NAND_CMD_READSTATUS 0x70
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# define NAND_CMD_COPYBACKPRG1 0x85
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# define NAND_IOSTATUS_ERROR (1 << 0)
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# define NAND_IOSTATUS_PLANE0 (1 << 1)
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# define NAND_IOSTATUS_PLANE1 (1 << 2)
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# define NAND_IOSTATUS_PLANE2 (1 << 3)
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# define NAND_IOSTATUS_PLANE3 (1 << 4)
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# define NAND_IOSTATUS_ERROR (1 << 0)
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# define NAND_IOSTATUS_PLANE0 (1 << 1)
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# define NAND_IOSTATUS_PLANE1 (1 << 2)
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# define NAND_IOSTATUS_PLANE2 (1 << 3)
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# define NAND_IOSTATUS_PLANE3 (1 << 4)
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# define NAND_IOSTATUS_READY (1 << 6)
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# define NAND_IOSTATUS_UNPROTCT (1 << 7)
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# define NAND_IOSTATUS_UNPROTCT (1 << 7)
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# define MAX_PAGE 0x800
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# define MAX_OOB 0x40
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# define MAX_PAGE 0x800
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# define MAX_OOB 0x40
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typedef struct NANDFlashState NANDFlashState;
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struct NANDFlashState {
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@ -102,40 +102,40 @@ static void mem_and(uint8_t *dest, const uint8_t *src, size_t n)
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}
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}
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# define NAND_NO_AUTOINCR 0x00000001
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# define NAND_BUSWIDTH_16 0x00000002
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# define NAND_NO_PADDING 0x00000004
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# define NAND_CACHEPRG 0x00000008
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# define NAND_COPYBACK 0x00000010
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# define NAND_IS_AND 0x00000020
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# define NAND_4PAGE_ARRAY 0x00000040
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# define NAND_NO_READRDY 0x00000100
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# define NAND_SAMSUNG_LP (NAND_NO_PADDING | NAND_COPYBACK)
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# define NAND_NO_AUTOINCR 0x00000001
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# define NAND_BUSWIDTH_16 0x00000002
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# define NAND_NO_PADDING 0x00000004
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# define NAND_CACHEPRG 0x00000008
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# define NAND_COPYBACK 0x00000010
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# define NAND_IS_AND 0x00000020
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# define NAND_4PAGE_ARRAY 0x00000040
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# define NAND_NO_READRDY 0x00000100
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# define NAND_SAMSUNG_LP (NAND_NO_PADDING | NAND_COPYBACK)
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# define NAND_IO
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# define PAGE(addr) ((addr) >> ADDR_SHIFT)
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# define PAGE_START(page) (PAGE(page) * (NAND_PAGE_SIZE + OOB_SIZE))
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# define PAGE_MASK ((1 << ADDR_SHIFT) - 1)
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# define OOB_SHIFT (PAGE_SHIFT - 5)
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# define OOB_SIZE (1 << OOB_SHIFT)
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# define SECTOR(addr) ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
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# define SECTOR_OFFSET(addr) ((addr) & ((511 >> PAGE_SHIFT) << 8))
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# define PAGE(addr) ((addr) >> ADDR_SHIFT)
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# define PAGE_START(page) (PAGE(page) * (NAND_PAGE_SIZE + OOB_SIZE))
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# define PAGE_MASK ((1 << ADDR_SHIFT) - 1)
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# define OOB_SHIFT (PAGE_SHIFT - 5)
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# define OOB_SIZE (1 << OOB_SHIFT)
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# define SECTOR(addr) ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
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# define SECTOR_OFFSET(addr) ((addr) & ((511 >> PAGE_SHIFT) << 8))
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# define NAND_PAGE_SIZE 256
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# define PAGE_SHIFT 8
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# define NAND_PAGE_SIZE 256
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# define PAGE_SHIFT 8
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# include "nand.c"
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# define NAND_PAGE_SIZE 512
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# define PAGE_SHIFT 9
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# define NAND_PAGE_SIZE 512
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# define PAGE_SHIFT 9
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# include "nand.c"
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# define NAND_PAGE_SIZE 2048
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# define PAGE_SHIFT 11
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# define PAGE_SECTORS 4
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# define ADDR_SHIFT 16
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# define NAND_PAGE_SIZE 2048
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# define PAGE_SHIFT 11
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# define PAGE_SECTORS 4
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# define ADDR_SHIFT 16
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# include "nand.c"
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/* Information based on Linux drivers/mtd/nand/raw/nand_ids.c */
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@ -148,79 +148,79 @@ static const struct {
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} nand_flash_ids[0x100] = {
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[0 ... 0xff] = { 0 },
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[0x6b] = { 4, 8, 9, 4, 0 },
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[0xe3] = { 4, 8, 9, 4, 0 },
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[0xe5] = { 4, 8, 9, 4, 0 },
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[0xd6] = { 8, 8, 9, 4, 0 },
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[0xe6] = { 8, 8, 9, 4, 0 },
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[0x6b] = { 4, 8, 9, 4, 0 },
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[0xe3] = { 4, 8, 9, 4, 0 },
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[0xe5] = { 4, 8, 9, 4, 0 },
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[0xd6] = { 8, 8, 9, 4, 0 },
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[0xe6] = { 8, 8, 9, 4, 0 },
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[0x33] = { 16, 8, 9, 5, 0 },
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[0x73] = { 16, 8, 9, 5, 0 },
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[0x43] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x53] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x33] = { 16, 8, 9, 5, 0 },
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[0x73] = { 16, 8, 9, 5, 0 },
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[0x43] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x53] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x35] = { 32, 8, 9, 5, 0 },
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[0x75] = { 32, 8, 9, 5, 0 },
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[0x45] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x55] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x35] = { 32, 8, 9, 5, 0 },
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[0x75] = { 32, 8, 9, 5, 0 },
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[0x45] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x55] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x36] = { 64, 8, 9, 5, 0 },
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[0x76] = { 64, 8, 9, 5, 0 },
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[0x46] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x56] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x36] = { 64, 8, 9, 5, 0 },
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[0x76] = { 64, 8, 9, 5, 0 },
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[0x46] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x56] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x78] = { 128, 8, 9, 5, 0 },
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[0x39] = { 128, 8, 9, 5, 0 },
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[0x79] = { 128, 8, 9, 5, 0 },
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[0x72] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x49] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x74] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x59] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x78] = { 128, 8, 9, 5, 0 },
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[0x39] = { 128, 8, 9, 5, 0 },
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[0x79] = { 128, 8, 9, 5, 0 },
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[0x72] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x49] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x74] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x59] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x71] = { 256, 8, 9, 5, 0 },
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[0x71] = { 256, 8, 9, 5, 0 },
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/*
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* These are the new chips with large page size. The pagesize and the
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* erasesize is determined from the extended id bytes
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*/
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# define LP_OPTIONS (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
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# define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
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# define LP_OPTIONS (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
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# define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
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/* 512 Megabit */
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[0xa2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xf2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xb2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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[0xc2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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[0xa2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xf2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xb2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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[0xc2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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/* 1 Gigabit */
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[0xa1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xf1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xb1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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[0xc1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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[0xa1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xf1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xb1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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[0xc1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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/* 2 Gigabit */
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[0xaa] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xda] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xba] = { 256, 16, 0, 0, LP_OPTIONS16 },
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[0xca] = { 256, 16, 0, 0, LP_OPTIONS16 },
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[0xaa] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xda] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xba] = { 256, 16, 0, 0, LP_OPTIONS16 },
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[0xca] = { 256, 16, 0, 0, LP_OPTIONS16 },
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/* 4 Gigabit */
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[0xac] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xdc] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xbc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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[0xcc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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[0xac] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xdc] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xbc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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[0xcc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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/* 8 Gigabit */
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[0xa3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xd3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xb3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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[0xc3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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[0xa3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xd3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xb3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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[0xc3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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/* 16 Gigabit */
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[0xa5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xd5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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[0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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[0xa5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xd5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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[0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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};
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static void nand_reset(DeviceState *dev)
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@ -812,4 +812,4 @@ static void glue(nand_init_, NAND_PAGE_SIZE)(NANDFlashState *s)
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# undef PAGE_SHIFT
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# undef PAGE_SECTORS
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# undef ADDR_SHIFT
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#endif /* NAND_IO */
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#endif /* NAND_IO */
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