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hw/sd/sdhci: Set reset value of interrupt registers

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The interrupt enable registers are not reset to 0 on Freescale eSDHC
but some bits are enabled on reset. At least some U-Boot versions seem
to expect this and not initialise these registers before expecting
interrupts. Use existing vendor property for Freescale eSDHC and set
the reset value of the interrupt registers to match Freescale
documentation.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20250210160329.DDA7F4E600E@zero.eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
BALATON Zoltan 2025-02-10 17:03:29 +01:00 • committed by Philippe Mathieu-Daudé
parent 825b96dbce
commit d060b2789f
3 changed files with 6 additions and 0 deletions
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1
include/hw/sd/sdhci.h
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@ -110,6 +110,7 @@ typedef struct SDHCIState SDHCIState;
#define SDHCI_VENDOR_NONE 0
#define SDHCI_VENDOR_IMX 1
#define SDHCI_VENDOR_FSL 2
/*
* Controller does not provide transfer-complete interrupt when not