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Hexagon (target/hexagon) Short-circuit more HVX single instruction packets

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The generated helpers for HVX use pass-by-reference, so they can't
short-circuit when the reads/writes overlap.  The instructions with
overrides are OK because they use tcg_gen_gvec_*.

We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs
to set the flag when the instruction is an HVX instruction with a
generated helper.

We add an override for V6_vcombine so that it can be short-circuited
along with a test case in tests/tcg/hexagon/hvx_misc.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-15-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2023-04-27 16:00:05 -07:00
parent b85529854e
commit d05d5eebc7
5 changed files with 65 additions and 2 deletions
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21
tests/tcg/hexagon/hvx_misc.c
View file

@ -454,6 +454,25 @@ static void test_load_cur_predicated(void)
check_output_w(__LINE__, BUFSIZE);
}
static void test_vcombine(void)
{
for (int i = 0; i < BUFSIZE / 2; i++) {
asm volatile("v2 = vsplat(%0)\n\t"
"v3 = vsplat(%1)\n\t"
"v3:2 = vcombine(v2, v3)\n\t"
"vmem(%2+#0) = v2\n\t"
"vmem(%2+#1) = v3\n\t"
:
: "r"(2 * i), "r"(2 * i + 1), "r"(&output[2 * i])
: "v2", "v3", "memory");
for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {
expect[2 * i].w[j] = 2 * i + 1;
expect[2 * i + 1].w[j] = 2 * i;
}
}
check_output_w(__LINE__, BUFSIZE);
}
int main()
{
init_buffers();
@ -494,6 +513,8 @@ int main()
test_load_tmp_predicated();
test_load_cur_predicated();
test_vcombine();
puts(err ? "FAIL" : "PASS");
return err ? 1 : 0;
}