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Hexagon (target/hexagon) Short-circuit more HVX single instruction packets

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The generated helpers for HVX use pass-by-reference, so they can't
short-circuit when the reads/writes overlap.  The instructions with
overrides are OK because they use tcg_gen_gvec_*.

We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs
to set the flag when the instruction is an HVX instruction with a
generated helper.

We add an override for V6_vcombine so that it can be short-circuited
along with a test case in tests/tcg/hexagon/hvx_misc.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-15-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2023-04-27 16:00:05 -07:00
parent b85529854e
commit d05d5eebc7
5 changed files with 65 additions and 2 deletions
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17
target/hexagon/translate.c
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@ -378,8 +378,20 @@ static bool need_commit(DisasContext *ctx)
return true;
}
if (pkt->num_insns == 1 && !pkt->pkt_has_hvx) {
return false;
if (pkt->num_insns == 1) {
if (pkt->pkt_has_hvx) {
/*
* The HVX instructions with generated helpers use
* pass-by-reference, so they need the read/write overlap
* check below.
* The HVX instructions with overrides are OK.
*/
if (!ctx->has_hvx_helper) {
return false;
}
} else {
return false;
}
}
/* Check for overlap between register reads and writes */
@ -454,6 +466,7 @@ static void analyze_packet(DisasContext *ctx)
{
Packet *pkt = ctx->pkt;
ctx->need_pkt_has_store_s1 = false;
ctx->has_hvx_helper = false;
for (int i = 0; i < pkt->num_insns; i++) {
Insn *insn = &pkt->insn[i];
ctx->insn = insn;